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1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers最新文献

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Diffusion-an analytic procedure applied to macro cell placement 扩散-应用于宏细胞放置的分析程序
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129852
C. Kyung, P. V. Kraus, D. Mlynski
{"title":"Diffusion-an analytic procedure applied to macro cell placement","authors":"C. Kyung, P. V. Kraus, D. Mlynski","doi":"10.1109/ICCAD.1990.129852","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129852","url":null,"abstract":"A description is presented of a novel optimization procedure called diffusion which can be used in global circuit placement for suppressing inter-module and module-to-chip boundary overlaps. A salient feature of the proposed diffusion procedure is that multiple decisions on the moves of all variables (module positions) are simultaneously made such that a global, analytic objective function is minimized. Various strategies are discussed to speed up the convergence, and to prevent the solution from being stuck at local minima. A net force model is used with the diffusion procedure to minimize the inter-module wire length besides reducing the inter-module and module-to-chip overlaps. Various experimental results are given. Further potential applications of the proposed procedure include multilayer placement, and placement in an arbitrarily-shaped region.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129249149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A robust framework for hierarchical floorplanning with integrated global wiring 一个强大的框架，分层地板规划与集成的全球布线
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129865
Thomas Lengauer, Rolf Müller
{"title":"A robust framework for hierarchical floorplanning with integrated global wiring","authors":"Thomas Lengauer, Rolf Müller","doi":"10.1109/ICCAD.1990.129865","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129865","url":null,"abstract":"A floorplanning system was implemented that is based on circuit partitioning and incorporates hierarchical global wiring. Besides unifying several existing ideas in floorplanning, the system introduces the following components: (1) a novel and more accurate estimate of wiring area during the floorplan sizing process and (2) a systematic optimization procedure during the selection of suitable floorplan patterns in the top-down phase that integrates floorplanning and hierarchical wiring. Experiments with the system prove the feasibility of the approach.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129243985","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
Measuring error propagation in waveform relaxation algorithms 测量波形松弛算法中的误差传播
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129871
C. Zukowski, G. Gristede, A. Ruehli
{"title":"Measuring error propagation in waveform relaxation algorithms","authors":"C. Zukowski, G. Gristede, A. Ruehli","doi":"10.1109/ICCAD.1990.129871","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129871","url":null,"abstract":"An analysis tool is introduced that measures subcircuit coupling and error attenuation in waveform relaxation (WR) circuit simulation algorithms with full dimensionality. Unlike current methods that use heuristics to calculate scalar gains, this method capture all the effects of error attenuation over time and space. An example is provided of how this technique can be used to study the performance of various partitions, schedules, and WR algorithms on a wide range of technologies, including BiCMOS.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115885234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Implicit state transition graphs: applications to sequential logic synthesis and test 隐式状态转换图:应用于顺序逻辑的综合和测试
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129847
P. Ashar, Abhijit Ghosh, S. Devadas, A. Newton
{"title":"Implicit state transition graphs: applications to sequential logic synthesis and test","authors":"P. Ashar, Abhijit Ghosh, S. Devadas, A. Newton","doi":"10.1109/ICCAD.1990.129847","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129847","url":null,"abstract":"Implicit state enumeration is used in developing strategies to solve key problems in sequential logic synthesis and test. It is shown that it is possible to extract implicit state transition graphs (ISTGs) from logic-gate and flip-flop descriptions of sequential circuits that allow equivalent states to be represented by cubes, and edges from different states to be coalesced into one, thereby decreasing significantly the CPU time and memory requirements of the extraction process. Coupled with the enumeration technique, synthesis strategies are proposed for FSMs (finite state machines) described at the logic level. As is illustrated, these synthesis strategies allow the authors to optimize large FSMs. The authors apply an ISTG traversal algorithm for verifying equivalence and detecting redundancies in logic-level sequential circuits. This algorithm is more efficient than previously developed sequential test generation algorithms when used to detect equivalent-state redundancies present in some classes of circuits.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128756609","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A timing-driven global router for custom chip design 为定制芯片设计的定时驱动的全局路由器
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129837
S. Prasitjutrakul, W. Kubitz
{"title":"A timing-driven global router for custom chip design","authors":"S. Prasitjutrakul, W. Kubitz","doi":"10.1109/ICCAD.1990.129837","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129837","url":null,"abstract":"A timing-driven global router is presented for custom chip design, whose objective is maximizing the minimum delay slack. Resistances and capacitances of interconnections, input gate capacitances and output driver resistance are used to approximate the interconnection delays during the routing. The router incrementally updates the delay at each sink pin of the signal obtained from the previous step during the routing. The maximum allowable delay at each sink pin (from a timing analyzer) along with the computed interconnection delays is used to guide the search process for the maximum-delay-slack route. It is shown that when the interconnection resistance is comparable to the output-driver resistance, minimizing the total net length is not always equivalent to minimizing the delay for a multiterminal net. The algorithm presented is experimentally shown to produce global routes achieving the objective.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133927742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 67
A routing algorithm for harvesting multipipeline arrays with small intercell and pipeline delays 一种获取具有小单元间和管道延迟的多管道阵列的路由算法
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129824
P. Koo, F. Lombardi, D. Sciuto
{"title":"A routing algorithm for harvesting multipipeline arrays with small intercell and pipeline delays","authors":"P. Koo, F. Lombardi, D. Sciuto","doi":"10.1109/ICCAD.1990.129824","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129824","url":null,"abstract":"A novel approach is analyzed for reconfiguring multipipeline arrays from two-dimensional arrays. The proposed approach is fully characterized and the conditions for switching and routing are given. A polynomial time complexity algorithm is proposed for the reconfiguration of multipipeline arrays. It is proved that 100% harvesting is possible using the proposed algorithm while achieving very small intercell and pipeline delays.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132842238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Fast switch-level fault simulation using functional fault modeling 使用功能故障建模快速开关级故障仿真
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129844
E. Vandris, G. Sobelman
{"title":"Fast switch-level fault simulation using functional fault modeling","authors":"E. Vandris, G. Sobelman","doi":"10.1109/ICCAD.1990.129844","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129844","url":null,"abstract":"A novel switch-level fault simulation method is presented for MOS circuits that combines compiled switch-level simulation techniques with functional fault modeling. The simulator models both node stuck-at-zero, stuck-at-one faults and transistor stuck-on, stuck-open faults. During compilation the switch-level circuit components are compiled into functional models. The effect of transistor faults on the function of the circuit components is modeled by functional fault models that execute very fast during simulation. The differential fault simulation algorithm developed for gate-level circuits is adapted for use at the switch-level and is shown to perform well, although it incurs a higher overhead due to the dynamic memory properties of MOS circuits.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134221096","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Implicit state enumeration of finite state machines using BDD's 使用BDD的有限状态机的隐式状态枚举
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129860
H. Touati, H. Savoj, Bill Lin, R. Brayton, A. Sangiovanni-Vincentelli
{"title":"Implicit state enumeration of finite state machines using BDD's","authors":"H. Touati, H. Savoj, Bill Lin, R. Brayton, A. Sangiovanni-Vincentelli","doi":"10.1109/ICCAD.1990.129860","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129860","url":null,"abstract":"The authors propose a novel method based on transition relations that only requires the ability to compute the BDD (binary decision diagram) for f/sub i/ and outperforms O. Coudert's (1990) algorithm for most examples. The method offers a simple notational framework to express the basic operations used in BDD-based state enumeration algorithms in a unified way and a set of techniques that can speed up range computation dramatically, including a variable ordering heuristic and a method based on transition relations.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134051007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 436
Race detection for two-phase systems 两相系统的竞赛检测
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129829
J. Grodstein, J. Montanaro, S. Marino
{"title":"Race detection for two-phase systems","authors":"J. Grodstein, J. Montanaro, S. Marino","doi":"10.1109/ICCAD.1990.129829","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129829","url":null,"abstract":"The authors present RACE2, a tool to find latch race-through in two-phase, non-underlapped-clock systems. Though these systems can run at very high clock speeds, susceptibility to race-through has made them difficult to design. RACE2, by detecting all race-through violations, greatly reduces the design risk on these very fast systems. It combines the exhaustive search of a pattern-independent tool with a knowledge base of fundamental principles about when races are-and are not-important. Planned enhancements include detection of saved-state races, detection of charge-share races, improved robustness, and better pruning methods for faster worst-case runtimes. For pieces of a large two-phase full-custom chip, CPU execution times are in minutes, seconds on a VAX-8800. To date, RACE2 has found five races in the chip, all of which were undetected by design reviews and logic simulation.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122568239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Floorplanning by topological constraint reduction 通过拓扑约束缩减进行平面规划
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129853
G. Vijayan, R. Tsay
{"title":"Floorplanning by topological constraint reduction","authors":"G. Vijayan, R. Tsay","doi":"10.1109/ICCAD.1990.129853","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129853","url":null,"abstract":"The problem considered is that of producing a legal floorplan that respects a given topological constraint set. The floorplanning approach described is targeted for multilayer sea-of-cells based designs. Therefore it is assumed that no channel separations are required between the blocks. The approach can be generalized to incorporate channel separations.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124984018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
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