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1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers最新文献

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SALSA: a new approach to scheduling with timing constraints SALSA:一种有时间限制的调度新方法
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129897
J. Nestor, Ganesh Krishnamoorthy
{"title":"SALSA: a new approach to scheduling with timing constraints","authors":"J. Nestor, Ganesh Krishnamoorthy","doi":"10.1109/ICCAD.1990.129897","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129897","url":null,"abstract":"First, an initial schedule that satisfies all timing constraints is generated using algorithms adapted from layout compaction. This schedule is then improved with respect to resource usage using simulated annealing. SALSA provides for efficient exploration of alternative schedules while supporting timing constraints, conditionals, loops, and subroutines. The SALSA scheduling procedure is described in detail. An implementation of the approach shows promising results.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126862533","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 86
A method for concurrent decomposition and factorization of Boolean expressions 布尔表达式的并发分解和因子分解方法
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129967
J. Vasudevamurthy, J. Rajski
{"title":"A method for concurrent decomposition and factorization of Boolean expressions","authors":"J. Vasudevamurthy, J. Rajski","doi":"10.1109/ICCAD.1990.129967","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129967","url":null,"abstract":"Efficient algorithms are described for decomposition and factorization of Boolean expressions. The method uses only two-literal single-cube divisors and double-cube divisors considered concurrently with their complementary expressions. It is demonstrated that these objects, despite their simplicity, provide a very good framework to reason about common algebraic divisors and the duality relations between expressions. The algorithm was implemented and excellent results on several benchmark circuits illustrate its efficiency and effectiveness.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"34 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133391449","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 59
Data path construction and refinement 数据路径的构建和细化
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129910
F. Tsai, Y. Hsu
{"title":"Data path construction and refinement","authors":"F. Tsai, Y. Hsu","doi":"10.1109/ICCAD.1990.129910","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129910","url":null,"abstract":"A system is described for the data path allocation problem in digital signal processor synthesis. The system, STAR, consists of three phases-preprocessing, data path construction (DPC), and data path refinement (DPR). The actions taken in each phase are described. The authors' contributions include the following: (1) theorems for the lower bound of the number of interconnections; (2) in the DPR phase, a more global view of the allocation problem is taken by ripping up and reallocating different types of objects simultaneously; (3) a novel technique to evaluate the binding quality of an object on the basis of a sharing of hardware resources which the object uses; (4) a method to judge the potential for upgrading a data path; and (5) an iterative improvement technique based on the idea of a relation network. The system currently supports the synthesis of architecture in linear topology and random topology. Parameters can be specified to explore different design alternatives and design space. Experiments on benchmarks show promising results.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"142 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123195325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 32
Timing optimization with testability considerations 考虑可测试性的时序优化
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129953
A. Saldanha, R. Brayton, A. Sangiovanni-Vincentelli, K. Cheng
{"title":"Timing optimization with testability considerations","authors":"A. Saldanha, R. Brayton, A. Sangiovanni-Vincentelli, K. Cheng","doi":"10.1109/ICCAD.1990.129953","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129953","url":null,"abstract":"Since redundancy is undesirable in high performance circuits, the authors explore timing optimization procedures to determine whether performance optimization may be achieved without introducing redundancy. They demonstrate the conditions under which timing optimization may introduce single stuck-fault redundancies into a given irredundant circuit and illustrate the difficulties in removing or preventing these redundancies. The authors then resolve the question of whether a testability criterion exists that may be retained or easily maintained as invariant during timing resynthesis.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"387 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124795461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Analysis of VLSI multiconductor systems by bi-level waveform relaxation VLSI多导体系统的双电平波形弛豫分析
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129870
Rui Wang, O. Wing
{"title":"Analysis of VLSI multiconductor systems by bi-level waveform relaxation","authors":"Rui Wang, O. Wing","doi":"10.1109/ICCAD.1990.129870","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129870","url":null,"abstract":"A novel algorithm to compute the transient response of a coupled, dispersive multiconductor system terminated in nonlinear loads such as transistors is developed. The characterization of the multiconductor system is obtained from a full-wave analysis based on the spectral domain approach, and it is suitable for circuit simulation. The transient response of such a system is computed by a bi-level waveform relaxation method. The solution process consists of two steps. One is to obtain a time domain solution at the input and output interfaces by local waveform relaxation, and the second is to transform the waveforms into the frequency domain and obtain the necessary updates for the next global relaxation step. The method allows the interconnects to be separated from the rest of the system so that both the nonlinear termination circuit and the multiconductor system can be analyzed in the most efficient way. The method has been applied to multiconductor systems terminated in MOS, ECL (emitter coupled logic), and GaAs transistors and it is shown that reflections and couplings can create logic errors in the system. The program that implements the algorithm is written in C.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121992085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
CheckT/sub c/ and minT/sub c/: timing verification and optimal clocking of synchronous digital circuits CheckT/sub c/和minT/sub c/:同步数字电路的定时验证和最佳时钟
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129979
K. Sakallah, T. Mudge, K. Olukotun
{"title":"CheckT/sub c/ and minT/sub c/: timing verification and optimal clocking of synchronous digital circuits","authors":"K. Sakallah, T. Mudge, K. Olukotun","doi":"10.1109/ICCAD.1990.129979","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129979","url":null,"abstract":"Two CAD tools, checkT/sub c/ and minT/sub c/, for timing verification and optimal clocking are introduced. Both tools are based on a new timing model of synchronous digital circuits. The model has the following features: (1) it is general enough to handle arbitrary multiphase clocking; (2) complete, in the sense that it captures signal propagation along short as well as long paths in the logic; (3) extensible to make it relatively easy to incorporate 'complex' latching structures; and (4) notationally simple to make it amenable to analytic treatment in some important special cases. These tools are being used to help in the design of a 4 ns gallium arsenide micro-supercomputer.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124058014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 112
Mixed-mode incremental simulation and concurrent fault simulation 混合模式增量仿真与并发故障仿真
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129868
Yun-Cheng Ju, Fred L. Yang, R. Saleh
{"title":"Mixed-mode incremental simulation and concurrent fault simulation","authors":"Yun-Cheng Ju, Fred L. Yang, R. Saleh","doi":"10.1109/ICCAD.1990.129868","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129868","url":null,"abstract":"A description is presented of efforts applying mixed-mode simulation techniques to two other areas of research. In incremental simulation, techniques are presented to perform fast incremental circuit simulation based on a modified incremental-in-space approach and event-driven techniques. In fault simulation, a mixed-mode fault simulator is presented that allows the user to specify any type of electrical level fault at the transistor level, as opposed to one of the simple stuck-at faults used in logic simulators. The program performs fault simulation, using mixed-mode techniques, and provides the fault coverage of a set of input patterns. To improve efficiency, concurrent fault simulation with a table look-up scheme is used. The merits of both algorithms are demonstrated with simulation results that show significant speed-ups over standard approaches.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126882859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A history model for managing the VLSI design process 管理超大规模集成电路设计过程的历史模型
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129924
T. Chiueh, R. Katz
{"title":"A history model for managing the VLSI design process","authors":"T. Chiueh, R. Katz","doi":"10.1109/ICCAD.1990.129924","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129924","url":null,"abstract":"A history model is proposed to support the dynamic aspects of VLSI design, i.e., the controlled and disciplined sequencing of CAD tool invocations. This model is based on a task specification language, for encapsulating CAD tool invocations, and a novel activity thread, which maintains the history of task invocations and serves as a focus for sharing work results in a cooperative manner. A prototype was built on top of the OCT CAD framework.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114966127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 33
A high-packing density module generator for bipolar analog LSIs 用于双极模拟lsi的高封装密度模块发生器
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129878
Y. Shiraishi, Mitsuyuki Kimura, Kazuhiko Kobayashi, Tetsuro Hino, Miki Seriuchi, M. Kusaoke
{"title":"A high-packing density module generator for bipolar analog LSIs","authors":"Y. Shiraishi, Mitsuyuki Kimura, Kazuhiko Kobayashi, Tetsuro Hino, Miki Seriuchi, M. Kusaoke","doi":"10.1109/ICCAD.1990.129878","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129878","url":null,"abstract":"Efficient placement and routing algorithms are presented for the modules of a bipolar analog LSI. In the layout of an analog module, a grid-free technique is required to minimize the module area and geometric constraint observance is necessary for the circuit performance optimization. The placement algorithm determines cell positions observing the geometric constraints by vertex-grouping of the constraint graph representing the relative device positions in the input circuit diagram. The routing algorithm, based on the characteristic fine-grid maze router, allows grid-free routing and variable width routings observing the geometric constraints by dynamically generating wiring prohibition. These algorithms are applied to the design of the analog modules. Automatically designed modules are compact and the performance requirements are met.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"26 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116655282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
A framework environment for logic design support system 逻辑设计支持系统的框架环境
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI: 10.1109/ICCAD.1990.129980
Kaname Kuroki, N. Nomizu, Shigenobu Suzuki, Kazutoshi Takahashi
{"title":"A framework environment for logic design support system","authors":"Kaname Kuroki, N. Nomizu, Shigenobu Suzuki, Kazutoshi Takahashi","doi":"10.1109/ICCAD.1990.129980","DOIUrl":"https://doi.org/10.1109/ICCAD.1990.129980","url":null,"abstract":"A framework for an integrated logic design support system is presented. Owing to the use of this framework, it is easy to develop and add commands which have variable functions for automated logic design. ILOS (integrated logic design system) has been developed using this framework. ILOS supports various design styles because these commands are flexibly combined in the framework. These commands are hierarchical circuit conversion, distributor synthesis, partitioned hierarchical design support, generation of schematic diagrams and logic synthesis, ILOS is used in the design of supercomputers, large-scale computers and medium-scale computers. In large-scale computer design, ILOS reduced manpower costs by 70%.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124578022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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