A hierarchical approach for testing large circuits

Abstract

A method and circuit are presented for implementing hierarchical scan. Hierarchical scan (HScan) has two parts: one is a methodology of adding scan type circuits to very large electronic designs in a novel fashion, such that the timing and real estate impact of scan is reduced, and the other is a scan circuit which serves the above methodology. The advantage of HScan is that it can analyze and improve testability on subunits of very large design such that the testability solution remains valid for the full scale design.<>