GRCA: a global approach for floorplanning synthesis in VLSI macrocell design

Abstract

A novel floorplanning method for the macrocell layout style is presented. The floorplan state space is characterized by an equivalence relation to apply efficient solution techniques. A pseudo-polynomial area optimization algorithm is proposed that derives the optimal slicing tree from a given hierarchical floorplan tree. The order of this floorplan tree is at least two and at most five. Extensions of this approach to cover non-slicing floorplans are also described. Since floorplanning and routing are inter-dependent tasks, an improved dynamic updating scheme is proposed to consider interconnect space around each cell during the floorplan assembly. The method has been successfully applied to an industrial design with about 260000 transistors.<>