跨锁存器边界的多级逻辑最小化

1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers Pub Date : 1990-11-11 DOI:10.1109/ICCAD.1990.129938

Y. Matsunaga, M. Fujita, Takeo Kakuda

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引用次数: 8

摘要

提出了一种最小化顺序电路的方法。它采用了顺序电路扩展的允许函数，并可以利用网络拓扑结构导出的无关函数。此外，通过向二进制决策图(BDD)引入指示时间标签的边缘属性，给出了扩展允许函数的有效二进制决策图(BDD)实现。采用该方法可以有效地减少含锁存器的电路。

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Multi-level logic minimization across latch boundaries

A method to minimize sequential circuits is presented. It uses permissible functions extended for sequential circuits, and can make use of don't cares derived from network topology. Also, an efficient binary decision diagram (BDD) implementation of the extended permissible functions is presented by introducing edge attributes that indicate time label to the BDD. Circuits including latches can be efficiently minimized with the proposed method.<>

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来源期刊

1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers

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