An O(n/sup 3/logn)-heuristic for microcode bit optimization

Abstract

The authors address the problem of minimizing the control ROM width, which is important in the design of microprogrammed processors, because it directly reduces the silicon area of the control unit. A heuristic algorithm is proposed which is based on graph partitioning. This algorithm results in nearly optimal solutions with the time complexity of O(n/sup 3/log n), where n denotes the number of distinct microoperations. Comparison of the results with earlier works shows that the proposed heuristic performs better in terms of cost and/or CPU time.<>