CADICS-cyclic analog-to-digital converter synthesis

Abstract

CADICS is a technology-independent synthesis tool for generating complete netlists and layouts for CMOS cyclic analog-to-digital converters from a set of specifications. The program is capable of synthesizing A/D converters which have a broad range of sampling rate, resolution (up to 12 bits plus sign bit), and silicon area, and performance comparable to a manual approach without using any standard cell libraries. At higher resolutions provisions for internal self-calibration or capacitor trim array are included automatically.<>