DC parameterized piecewise-function transistor models for bipolar and MOS logic stage delay evaluation

A novel technique is presented for analyzing nonlinear active devices driving RC trees which accounts for nonlinear behavior in such a way that the accuracy obtained is typically within 10% of SPICE. This is achieved with a tremendous savings in calculation time as compared to SPICE, using exclusively DC parameterized transistor models. These models have been included in a prototype program for analyzing bipolar and CMOS logic-stage delay models. These techniques are currently being extended to provide best-case and worst-case delay approximations in terms of the DC parameterized piecewise-linear and piecewise-quadratic Thevenin models.<>