{"title":"电容耦合错误检查器","authors":"W. Grundmann, Y. Yen","doi":"10.1109/ICCAD.1990.129892","DOIUrl":null,"url":null,"abstract":"Capacitive coupling among critical nodes in a CMOS VLSI circuit can cause disastrous effects on the logical operation of the circuit. At present, the only simulation method that can accurately detect global capacitive coupling errors is the classical circuit simulation, which, due to its limited capacity, is not practical to apply to the entire design. A pattern-independent circuit verification tool, XREF, is presented which can detect and report all possible failures in a design due to capacitive coupling effects.<<ETX>>","PeriodicalId":242666,"journal":{"name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","volume":"25 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"XREF coupling: capacitive coupling error checker\",\"authors\":\"W. Grundmann, Y. Yen\",\"doi\":\"10.1109/ICCAD.1990.129892\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Capacitive coupling among critical nodes in a CMOS VLSI circuit can cause disastrous effects on the logical operation of the circuit. At present, the only simulation method that can accurately detect global capacitive coupling errors is the classical circuit simulation, which, due to its limited capacity, is not practical to apply to the entire design. A pattern-independent circuit verification tool, XREF, is presented which can detect and report all possible failures in a design due to capacitive coupling effects.<<ETX>>\",\"PeriodicalId\":242666,\"journal\":{\"name\":\"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers\",\"volume\":\"25 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1990-11-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCAD.1990.129892\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCAD.1990.129892","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Capacitive coupling among critical nodes in a CMOS VLSI circuit can cause disastrous effects on the logical operation of the circuit. At present, the only simulation method that can accurately detect global capacitive coupling errors is the classical circuit simulation, which, due to its limited capacity, is not practical to apply to the entire design. A pattern-independent circuit verification tool, XREF, is presented which can detect and report all possible failures in a design due to capacitive coupling effects.<>
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