Proceedings of SEMI Advanced Semiconductor Manufacturing Conference and Workshop最新文献_第2页

Partnering for the integration of equipment recipe services into an automated factory 合作将设备配方服务集成到自动化工厂中

Proceedings of SEMI Advanced Semiconductor Manufacturing Conference and Workshop Pub Date : 1995-11-13 DOI: 10.1109/ASMC.1995.484349

J. Achacoso, G. Pisapía

引用次数: 3

Advancements in wafer finishing manufacturing technology involving plating 包括电镀在内的晶圆精加工技术的进展

Proceedings of SEMI Advanced Semiconductor Manufacturing Conference and Workshop Pub Date : 1995-11-13 DOI: 10.1109/ASMC.1995.484330

K. Lowry, C. VanHorn, G. Shawhan

{"title":"Advancements in wafer finishing manufacturing technology involving plating","authors":"K. Lowry, C. VanHorn, G. Shawhan","doi":"10.1109/ASMC.1995.484330","DOIUrl":"https://doi.org/10.1109/ASMC.1995.484330","url":null,"abstract":"Summary form only given. Momentum for the increased use of plating processes in wafer finishing applications, as an alternative to vapor deposition technology, is occurring in both bump applications and also as a potential replacement to the top layer conductors of the integrated circuit itself. The acceptance of plating technology in the semiconductor industry is predicated upon its ability to satisfy both key technical requirements and, at the same time, effectively address cost of ownership issues. This is especially true for larger area format production where the facility investment required for implementation necessitates significant improvement in all areas of process cost. In general, electroplating offers advantages in both of these areas. This paper discusses new automated, cassette-to-cassette electroplating equipment that has been developed specifically for wafer finishing applications. Included in the presentation will be details of the automation of the system and the expected throughput capabilities for high volume production including 200 mm wafers. Additional cost of ownership issues will be discussed including fixed cost estimates over the life of the system, variable cost estimates relating to the annual operation of the system, system utilization and downtime estimates and process consistency as it relates to potential yield losses. Results of distribution studies on 200 mm wafers carried out in this equipment will also be presented. In particular, electroplated copper, which has its primary application as a conductor replacement for vapor deposited aluminum on the IC itself will be discussed. In addition, lead-tin will also be discussed as it relates to wafer bumping for flip-chip applications. Information will also be included on gold bumping for TAB applications.","PeriodicalId":237741,"journal":{"name":"Proceedings of SEMI Advanced Semiconductor Manufacturing Conference and Workshop","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116840436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Spatial yield modeling for semiconductor wafers 半导体晶圆的空间良率模型

Proceedings of SEMI Advanced Semiconductor Manufacturing Conference and Workshop Pub Date : 1995-11-13 DOI: 10.1109/ASMC.1995.484386

A. Mirza, G. O'Donoghue, A. W. Drake, S. Graves

{"title":"Spatial yield modeling for semiconductor wafers","authors":"A. Mirza, G. O'Donoghue, A. W. Drake, S. Graves","doi":"10.1109/ASMC.1995.484386","DOIUrl":"https://doi.org/10.1109/ASMC.1995.484386","url":null,"abstract":"The distribution of good and bad chips on a semiconductor wafer typically results in two types of regions, one that contains both good and bad chips distributed in a random fashion, called a \"non-zero yield region\", and the other that contains almost all bad chips, called a \"zero yield region\". The yield of a non-zero yield region is modeled by well understood expressions derived from Poisson or negative binomial statistics. To account for yield loss associated with zero yield regions, the yield expression for non-zero yield regions is multiplied by Y/sub 0/, the fraction of the wafer occupied by non-zero yield regions. The presence, extent, and nature of zero yield regions on a given wafer provide information about yield loss mechanisms responsible for causing them. Two statistical methods are developed to detect the presence of zero yield regions and calculate Y/sub 0/ for a given wafer. These methods are based on a set-theoretic image analysis tool, called the Aura Framework, and on hypothesis testing on nearest neighbors of bad chips. Results show that the modeling of the distribution of good and bad chips on wafers in terms of zero and non-zero yield regions is highly accurate. The detection of zero yield regions provides improved insight into the yield loss mechanisms. Also, the ability to calculate Y/sub 0/ enables better evaluation of the yield models used to predict the yield of non-zero yield regions.","PeriodicalId":237741,"journal":{"name":"Proceedings of SEMI Advanced Semiconductor Manufacturing Conference and Workshop","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125034133","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15

Experiences with SMIF-integration for semiconductor fabrication 具有半导体制造smif集成经验

Proceedings of SEMI Advanced Semiconductor Manufacturing Conference and Workshop Pub Date : 1995-11-13 DOI: 10.1109/ASMC.1995.484409

B. Klumpp, J. Schliesser, O. Herzog, P. Staudt-Fischbach

引用次数: 0

A yield based replacement for capability indexes 一种基于产量的能力指标替代方案

Proceedings of SEMI Advanced Semiconductor Manufacturing Conference and Workshop Pub Date : 1995-11-13 DOI: 10.1109/ASMC.1995.484372

R. Abugov, X. J. Dietrich

引用次数: 1

Yield enhancement using a memory expert system linked to the wafer inspection tool 利用与晶圆检测工具相连接的存储器专家系统提高良率

Proceedings of SEMI Advanced Semiconductor Manufacturing Conference and Workshop Pub Date : 1995-11-13 DOI: 10.1109/ASMC.1995.484387

M. Sugimoto, H. Hamada

引用次数: 5

Cycle time metrics for R&D semiconductor wafer fabrication 研发半导体晶圆制造的周期时间指标

Proceedings of SEMI Advanced Semiconductor Manufacturing Conference and Workshop Pub Date : 1995-11-13 DOI: 10.1109/ASMC.1995.484350

N. Pierce, A. Yost

引用次数: 2

ISPM characterization of gas phase nucleation in a Novellus C1 WCVD process chamber Novellus C1 WCVD工艺室气相成核的ISPM表征

Proceedings of SEMI Advanced Semiconductor Manufacturing Conference and Workshop Pub Date : 1995-11-13 DOI: 10.1109/ASMC.1995.484331

T. Winter, D. Colston, E. Mickler, R. Woodward, M. Kimmich, T. Green

{"title":"ISPM characterization of gas phase nucleation in a Novellus C1 WCVD process chamber","authors":"T. Winter, D. Colston, E. Mickler, R. Woodward, M. Kimmich, T. Green","doi":"10.1109/ASMC.1995.484331","DOIUrl":"https://doi.org/10.1109/ASMC.1995.484331","url":null,"abstract":"An High Yield Technology model 70 in-situ particle monitor (ISPM) has been installed on the pumpline of a Novellus C1 WCVD process chamber in an effort to better characterize and control the particle performance of the chamber, especially as it pertains to gas phase nucleation (GPN) in the tool. GPN results when the SiH/sub 4/:WF/sub 6/ ratio exceeds 1:1 at the system operating pressure and temperature. During experimentation the GPN boundary conditions were identified and the factors which controlled the phenomena were explored. The ISPM was used to detect the occurrence of a GPN event. A good correlation between high ISPM counts and in-film particles was established. The ISPM was a crucial element in identifying process boundary conditions as they related to GPN; this in turn helped assure control of the process wafers. An additional effect was noted as relates to formation and deposition of the nucleation sites on the wafer. In a two wafer test GPN was purposely generated, with the ISPM detecting comparable levels of particles during the processing of both wafers; however, very few particles were detected on the first wafer whereas several hundred particles were detected on the second wafer. This effect has been attributed to thermophoretic effects protecting the first wafer, with the second wafer being contaminated before it was heated.","PeriodicalId":237741,"journal":{"name":"Proceedings of SEMI Advanced Semiconductor Manufacturing Conference and Workshop","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132533476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Temperature controlling with reflexion supported pyrometric interferometry (RSPI) at rapid thermal chemical vapor deposition-facilities (RTCVD) 快速热化学气相沉积装置(RTCVD)中反射支持热测量干涉法(RSPI)的温度控制

Proceedings of SEMI Advanced Semiconductor Manufacturing Conference and Workshop Pub Date : 1995-11-13 DOI: 10.1109/ASMC.1995.484360

J. Maeritz, H. Moller, F.G. Bobel, D. Ritter, M. Weusthof, J. Holleman

{"title":"Temperature controlling with reflexion supported pyrometric interferometry (RSPI) at rapid thermal chemical vapor deposition-facilities (RTCVD)","authors":"J. Maeritz, H. Moller, F.G. Bobel, D. Ritter, M. Weusthof, J. Holleman","doi":"10.1109/ASMC.1995.484360","DOIUrl":"https://doi.org/10.1109/ASMC.1995.484360","url":null,"abstract":"Summary form only given. RTCVD-facilities aspire to be one of the most used production tools in high yield semiconductor manufacturing in the next years. To obtain best quality electronic devices with a great flexibility it is necessary to observe and control many process parameters. Temperature and film thickness are two of these quantities. Since RSPI is an established real time tool for in-situ temperature and film thickness evaluation at many wafer production facilities, the task was to extend its applicability to RTCVD-facilities. To overcome optical irradiation of RTP-sources infrared RSPI adaptions were made in the wavelength region of 1.5 /spl mu/m. The measurement equipment according to RTCVD-facilities is compared with the standard RSPI-setup. In this paper data of temperature and film growth measurements are presented in dependence of various material compositions and observation wavelength. It is shown that the lowest measurable temperature with a minimal resolution 1/spl deg/C is about 380/spl deg/C up to 450/spl deg/C depending on the wafer material and observation wavelength. Beyond temperature and film thickness evaluation we succeeded in the first temperature controlling during film with RSPI-methods at RTCVD-facilities. The paper also demonstrates growth rates of films are held much more constant with temperature control in comparison to deposition procedures without temperature control. Material compositions of the discussed data are Poly-Si on Si; Si on Ge; SiN on Si and so on.","PeriodicalId":237741,"journal":{"name":"Proceedings of SEMI Advanced Semiconductor Manufacturing Conference and Workshop","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133511802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

COS-based Q-V testing: in-line options for oxide charge monitoring 基于cos的Q-V测试:用于氧化电荷监测的在线选项

Proceedings of SEMI Advanced Semiconductor Manufacturing Conference and Workshop Pub Date : 1995-11-13 DOI: 10.1109/ASMC.1995.484342

G. Horner, M. Fung, R.L. Verkuil, T. G. Miller

引用次数: 4