Advancements in wafer finishing manufacturing technology involving plating

Abstract

Summary form only given. Momentum for the increased use of plating processes in wafer finishing applications, as an alternative to vapor deposition technology, is occurring in both bump applications and also as a potential replacement to the top layer conductors of the integrated circuit itself. The acceptance of plating technology in the semiconductor industry is predicated upon its ability to satisfy both key technical requirements and, at the same time, effectively address cost of ownership issues. This is especially true for larger area format production where the facility investment required for implementation necessitates significant improvement in all areas of process cost. In general, electroplating offers advantages in both of these areas. This paper discusses new automated, cassette-to-cassette electroplating equipment that has been developed specifically for wafer finishing applications. Included in the presentation will be details of the automation of the system and the expected throughput capabilities for high volume production including 200 mm wafers. Additional cost of ownership issues will be discussed including fixed cost estimates over the life of the system, variable cost estimates relating to the annual operation of the system, system utilization and downtime estimates and process consistency as it relates to potential yield losses. Results of distribution studies on 200 mm wafers carried out in this equipment will also be presented. In particular, electroplated copper, which has its primary application as a conductor replacement for vapor deposited aluminum on the IC itself will be discussed. In addition, lead-tin will also be discussed as it relates to wafer bumping for flip-chip applications. Information will also be included on gold bumping for TAB applications.