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2011 41st IEEE International Symposium on Multiple-Valued Logic最新文献

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Information-Preserving Logic Based on Logical Reversibility to Reduce the Memory Data Transfer Bottleneck and Heat Dissipation 基于逻辑可逆性的信息保存逻辑减少内存数据传输瓶颈和散热
2011 41st IEEE International Symposium on Multiple-Valued Logic Pub Date : 2011-05-23 DOI: 10.1109/ISMVL.2011.43
M. Lukac, B. Shuai, M. Kameyama, D. Michael Miller
{"title":"Information-Preserving Logic Based on Logical Reversibility to Reduce the Memory Data Transfer Bottleneck and Heat Dissipation","authors":"M. Lukac, B. Shuai, M. Kameyama, D. Michael Miller","doi":"10.1109/ISMVL.2011.43","DOIUrl":"https://doi.org/10.1109/ISMVL.2011.43","url":null,"abstract":"We present an approach to the cache bottleneck problem using reversible logic circuits. The high traffic between the cache and the main memory in current systems considerably slows down the performance of the general information processing unit (IPU). Moreover this high traffic has the consequence of high heat generation in VLSI elements such as the CPU or dedicated processors. Thus the reduction in use or complete removal of the cache memory could be beneficial to current processors architecture. We present a model where the IPU is designed as a logically reversible circuit. This allows one to reduce the cachememory traffic because data can be recovered using the output of the current processing. We illustrate the implementation of the approach by providing a design of an adiabatic reversible Toffoli gate with a power consumption equivalent to a classical adiabatic circuit. With these approaches, the cache-memory bottleneck and heat dissipation can potentially be reduced even by using only logically reversible circuit implementation.","PeriodicalId":234611,"journal":{"name":"2011 41st IEEE International Symposium on Multiple-Valued Logic","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131233599","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Weak Uninorm Based Logic and Its Filter Theory 基于弱一致的逻辑及其滤波理论
2011 41st IEEE International Symposium on Multiple-Valued Logic Pub Date : 2011-05-23 DOI: 10.1109/ISMVL.2011.60
M. Kondo, M. Kawaguchi, M. Miyakoshi, O. Watari
{"title":"Weak Uninorm Based Logic and Its Filter Theory","authors":"M. Kondo, M. Kawaguchi, M. Miyakoshi, O. Watari","doi":"10.1109/ISMVL.2011.60","DOIUrl":"https://doi.org/10.1109/ISMVL.2011.60","url":null,"abstract":"We give an axiomatic system of a logic called here a weak uninorm based logic (wUL), which is proved to be characterized by the class of all (not necessary bounded nor integral) commutative residuated lattices. We see that the logic is algebraizable. Since many well-known logics, e.g., UBL by Watari and al., UL by Metcalfe and Montanga, ML by H\"ohle, MTL by Esteva and L. Godo, BL by H'ajek, and so on, are axiomatic extensions of our logic, those logics are all algebraizable. Moreover we define filters of commutative residuated lattices $X$ and show that the class of all filters of $X$ is isomorphic to the class $Con(X)$ of all congruences on $X$. At last, as an application of our characterization of wUL, we give a negative answer to the problem that \"Is UBL characterized by the class of linearly ordered UBL-algebras?\", which was left open in [10].","PeriodicalId":234611,"journal":{"name":"2011 41st IEEE International Symposium on Multiple-Valued Logic","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123784916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Using Multiple-Valued Logic Decision Diagrams to Model System Threat Probabilities 用多值逻辑决策图建模系统威胁概率
2011 41st IEEE International Symposium on Multiple-Valued Logic Pub Date : 2011-05-23 DOI: 10.1109/ISMVL.2011.12
T. Manikas, M. Thornton, D. Y. Feinstein
{"title":"Using Multiple-Valued Logic Decision Diagrams to Model System Threat Probabilities","authors":"T. Manikas, M. Thornton, D. Y. Feinstein","doi":"10.1109/ISMVL.2011.12","DOIUrl":"https://doi.org/10.1109/ISMVL.2011.12","url":null,"abstract":"System security continues to be of increasing importance. To effectively address both natural and intentional threats to large systems, the threats must be cataloged and analyzed. Extremely large and complex systems can have an accordingly large number of threat scenarios. Simply listing the threats and devising countermeasures for each is ineffective and not efficient. We describe a threat cataloging methodology whereby a large number of threats can be efficiently cataloged and analyzed for common features. This allows countermeasures to be formulated that address a large number of threats that share common features. The methodology utilizes Multiple-Valued Logic for describing the state of a large system and a multiple-valued decision diagram (MDD) for the threat catalog and analysis.","PeriodicalId":234611,"journal":{"name":"2011 41st IEEE International Symposium on Multiple-Valued Logic","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122057083","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Galois Theory for Partial Clones and Some Relational Clones 部分克隆和一些关系克隆的伽罗瓦理论
2011 41st IEEE International Symposium on Multiple-Valued Logic Pub Date : 2011-05-23 DOI: 10.1109/ISMVL.2011.14
Karsten Schölzel
{"title":"Galois Theory for Partial Clones and Some Relational Clones","authors":"Karsten Schölzel","doi":"10.1109/ISMVL.2011.14","DOIUrl":"https://doi.org/10.1109/ISMVL.2011.14","url":null,"abstract":"A Galois connection between partial clones and a new variant of relation algebras is established. We introduce a new elementary operation on relations which captures the difference between total and partial clones and allows us to adapt the proof of the Galois connection from the total case to the partial case. This Galois connection is able to capture all partial clones and is not restricted to strong partial clones as in previous work.","PeriodicalId":234611,"journal":{"name":"2011 41st IEEE International Symposium on Multiple-Valued Logic","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126811772","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An Error Correction Method for Binary and Multiple-Valued Logic 二值和多值逻辑的误差校正方法
2011 41st IEEE International Symposium on Multiple-Valued Logic Pub Date : 2011-05-23 DOI: 10.1109/ISMVL.2011.52
C. Winstead, Yi Luo, E. Monzon, Abiezer Tejeda
{"title":"An Error Correction Method for Binary and Multiple-Valued Logic","authors":"C. Winstead, Yi Luo, E. Monzon, Abiezer Tejeda","doi":"10.1109/ISMVL.2011.52","DOIUrl":"https://doi.org/10.1109/ISMVL.2011.52","url":null,"abstract":"This paper presents a method and circuit for correcting faults in logic systems. The method, called \"restorative feedback\" (RFB), is similar in some respects to triple modular redundancy (TMR), but has an improved error probability with respect to transient errors. Simulation results indicate an improvement by about two orders of magnitude compared to traditional TMR. CMOS circuits are presented for implementing restorative feedback. For binary logic, a dynamic CMOS circuit is considered. For multiple-valued logic, a semi-floating gate implementation is presented.","PeriodicalId":234611,"journal":{"name":"2011 41st IEEE International Symposium on Multiple-Valued Logic","volume":"257 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132806073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Synthesis Techniques for Ternary Quantum Logic 三元量子逻辑的综合技术
2011 41st IEEE International Symposium on Multiple-Valued Logic Pub Date : 2011-05-23 DOI: 10.1109/ISMVL.2011.55
S. B. Mandal, A. Chakrabarti, S. Sur-Kolay
{"title":"Synthesis Techniques for Ternary Quantum Logic","authors":"S. B. Mandal, A. Chakrabarti, S. Sur-Kolay","doi":"10.1109/ISMVL.2011.55","DOIUrl":"https://doi.org/10.1109/ISMVL.2011.55","url":null,"abstract":"Synthesis of ternary quantum circuits involves basic ternary gates and logic operations in the ternary quantum domain. Works that define ternary algebra and their applications for ternary quantum logic realization, are very few. In this paper, we express a ternary logic function in terms of projection operations including a new one. We demonstrate how to realize a few new multi-qutrit ternary gates in terms of generalized ternary gates and projection operations. We then employ our synthesis method to design ternary adder circuits which have better cost than that obtained by earlier method.","PeriodicalId":234611,"journal":{"name":"2011 41st IEEE International Symposium on Multiple-Valued Logic","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121243610","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
Notes on the Exclusive Disjunction 关于不相容析取的注释
2011 41st IEEE International Symposium on Multiple-Valued Logic Pub Date : 2011-05-23 DOI: 10.1109/ISMVL.2011.50
I. García-Honrado, E. Trillas
{"title":"Notes on the Exclusive Disjunction","authors":"I. García-Honrado, E. Trillas","doi":"10.1109/ISMVL.2011.50","DOIUrl":"https://doi.org/10.1109/ISMVL.2011.50","url":null,"abstract":"This short paper just contains some reflections on the symmetric difference operator translating into an algebraic framework the connective exclusive disjunction, the linguistic either/or. In particular, it tries to find an upper bound for the fuzzy operators generalizing the classical symmetric difference, that is, those to deal with imprecise statements. This search is made throughout the preservation of the inferential schemes of disjunctive syllogism in fuzzy logic. The paper tries to stress the inferential interest of the symmetric difference.","PeriodicalId":234611,"journal":{"name":"2011 41st IEEE International Symposium on Multiple-Valued Logic","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130601093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Paradigms for Many-sorted Non-classical Substitutions 多排序非经典替代的范式
2011 41st IEEE International Symposium on Multiple-Valued Logic Pub Date : 2011-05-23 DOI: 10.1109/ISMVL.2011.10
P. Eklund, Robert Helgesson, María Ángeles Galán García, J. Kortelainen
{"title":"Paradigms for Many-sorted Non-classical Substitutions","authors":"P. Eklund, Robert Helgesson, María Ángeles Galán García, J. Kortelainen","doi":"10.1109/ISMVL.2011.10","DOIUrl":"https://doi.org/10.1109/ISMVL.2011.10","url":null,"abstract":"We present three paradigms for non-classical substitution in a many-sorted context. Such an exposition has previously been demonstrated in the unsorted case but its extension is far from trivial. The first paradigm, classical many-sorted substitution taking variables to terms, is traditionally presented in a rather informal and \"verbal\" manner but we find that a strict categorical formulation is necessary to pave the way for non-classical extensions. The second paradigm provides substitution of variables for many-valued sets of terms and relies heavily on functors and monads over the category of indexed sets. Finally, in the third paradigm, we establish full non-classical substitution of many-valued sets of variables by many-valued sets of terms. The third paradigm has the category of many-valued indexed sets as its underlying category. These paradigms ensures transparency of the underlying categories and also makes a clear distinction between set-theoretic operation in the meta language and operations on sets and many-valued sets as found within respective underlying categories.","PeriodicalId":234611,"journal":{"name":"2011 41st IEEE International Symposium on Multiple-Valued Logic","volume":"313 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124247006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
The Lattice of the Clones of Self-Dual Functions in Three-Valued Logic 三值逻辑中自对偶函数克隆的格
2011 41st IEEE International Symposium on Multiple-Valued Logic Pub Date : 2011-05-23 DOI: 10.1109/ISMVL.2011.16
Dmitriy Zhuk
{"title":"The Lattice of the Clones of Self-Dual Functions in Three-Valued Logic","authors":"Dmitriy Zhuk","doi":"10.1109/ISMVL.2011.16","DOIUrl":"https://doi.org/10.1109/ISMVL.2011.16","url":null,"abstract":"The lattice of all clones of self-dual functions in three-valued logic is described in the paper. Even though this lattice contains a continuum of clones, a simple description was found. Using this description different properties of the lattice and of the clones were derived. Pair wise inclusion of the clones into each other was described, and all finitely generated clones were found. Also, for each clone the relation degree, the cardinality of the set of all clones containing this clone, and the cardinality of the set of all clones that are contained in this clone were determined.","PeriodicalId":234611,"journal":{"name":"2011 41st IEEE International Symposium on Multiple-Valued Logic","volume":"258 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115871846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Ultra Low-Voltage and High-Speed CMOS Full Adder Using Floating-Gates and Multiple-Valued Logic 基于浮门和多值逻辑的超低压高速CMOS全加法器
2011 41st IEEE International Symposium on Multiple-Valued Logic Pub Date : 2011-05-23 DOI: 10.1109/ISMVL.2011.11
Y. Berg
{"title":"Ultra Low-Voltage and High-Speed CMOS Full Adder Using Floating-Gates and Multiple-Valued Logic","authors":"Y. Berg","doi":"10.1109/ISMVL.2011.11","DOIUrl":"https://doi.org/10.1109/ISMVL.2011.11","url":null,"abstract":"In this paper we present a novel high speed and ultra low-voltage full adder circuit based on ultra low-voltage semi floating-gate CMOS logic. The full adder circuit contains a high speed ultraslow-voltage carry generator circuit and a multiple-valued intermediate representation of the summation. The full adder is suitable for low-voltage serial full adder design. Simulated data presented is valid for a 90nm TSMC CMOS process.","PeriodicalId":234611,"journal":{"name":"2011 41st IEEE International Symposium on Multiple-Valued Logic","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126180312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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