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2011 41st IEEE International Symposium on Multiple-Valued Logic最新文献

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Mapping Decision Diagrams for Multiple-Valued Logic Functions into Threshold Logic Networks 多值逻辑函数决策图映射到阈值逻辑网络
2011 41st IEEE International Symposium on Multiple-Valued Logic Pub Date : 2011-05-23 DOI: 10.1109/ISMVL.2011.28
M. Stankovic, S. Stojkovic, C. Moraga
{"title":"Mapping Decision Diagrams for Multiple-Valued Logic Functions into Threshold Logic Networks","authors":"M. Stankovic, S. Stojkovic, C. Moraga","doi":"10.1109/ISMVL.2011.28","DOIUrl":"https://doi.org/10.1109/ISMVL.2011.28","url":null,"abstract":"The paper presents a method for threshold logic realization of multiple valued functions through decision diagrams. New threshold logic modules convenient for mapping to decision diagrams are introduced and it is shown that these modules allow to reduce the complexity of the realization by using heterogeneous decision diagrams.","PeriodicalId":234611,"journal":{"name":"2011 41st IEEE International Symposium on Multiple-Valued Logic","volume":"266 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121668345","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Extending Multiple-Valued Clausal Forms with Linear Integer Arithmetic 用线性整数算法扩展多值子句形式
2011 41st IEEE International Symposium on Multiple-Valued Logic Pub Date : 2011-05-23 DOI: 10.1109/ISMVL.2011.53
C. Ansótegui, Miquel Bofill, F. Manyà, Mateu Villaret
{"title":"Extending Multiple-Valued Clausal Forms with Linear Integer Arithmetic","authors":"C. Ansótegui, Miquel Bofill, F. Manyà, Mateu Villaret","doi":"10.1109/ISMVL.2011.53","DOIUrl":"https://doi.org/10.1109/ISMVL.2011.53","url":null,"abstract":"We extend the language of signed many-valued clausal forms with linear integer arithmetic constraints. In this way, we get a simple modeling language in which a wide range of practical combinatorial problems admit compact and natural encodings. We then define efficient translations from our language into the SAT and SMT formalism, and propose to use SAT and SMT solvers for finding solutions.","PeriodicalId":234611,"journal":{"name":"2011 41st IEEE International Symposium on Multiple-Valued Logic","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133474572","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Designing a RISC CPU in Reversible Logic 可逆逻辑下RISC CPU的设计
2011 41st IEEE International Symposium on Multiple-Valued Logic Pub Date : 2011-05-23 DOI: 10.1109/ISMVL.2011.39
R. Wille, Mathias Soeken, Daniel Große, Eleonora Schönborn, R. Drechsler
{"title":"Designing a RISC CPU in Reversible Logic","authors":"R. Wille, Mathias Soeken, Daniel Große, Eleonora Schönborn, R. Drechsler","doi":"10.1109/ISMVL.2011.39","DOIUrl":"https://doi.org/10.1109/ISMVL.2011.39","url":null,"abstract":"Driven by its promising applications, reversible logic received significant attention. As a result, an impressive progress has been made in the development of synthesis approaches, implementation of sequential elements, and hardware description languages. In this paper, these recent achievements are employed in order to design a RISC CPU in reversible logic that can execute software programs written in an assembler language. The respective combinational and sequential components are designed using state-of-the-art design techniques.","PeriodicalId":234611,"journal":{"name":"2011 41st IEEE International Symposium on Multiple-Valued Logic","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128090535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
A Three-Valued Approach to the Master Argument 主论证的三值方法
2011 41st IEEE International Symposium on Multiple-Valued Logic Pub Date : 2011-05-23 DOI: 10.1109/ISMVL.2011.8
S. Akama, Y. Nagata
{"title":"A Three-Valued Approach to the Master Argument","authors":"S. Akama, Y. Nagata","doi":"10.1109/ISMVL.2011.8","DOIUrl":"https://doi.org/10.1109/ISMVL.2011.8","url":null,"abstract":"The Master Argument due to Diodorus Cronos claims that nothing is possible that neither is true nor will be true and that therefore every (present) possibility must be realized at a present or future time. Unfortunately, it leads to logical determinism. In this paper, based on Prior's insight, a three-valued approach to the Master Argument is presented by developing a three-valued modal tense logic with a Kripke semantics. We also discuss philosophical and logical issues in connection with other approaches.","PeriodicalId":234611,"journal":{"name":"2011 41st IEEE International Symposium on Multiple-Valued Logic","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132896867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Autosymmetric Multiple-Valued Functions: Theory and Spectral Characterization 自对称多值函数:理论与谱表征
2011 41st IEEE International Symposium on Multiple-Valued Logic Pub Date : 2011-05-23 DOI: 10.1109/ISMVL.2011.13
A. Bernasconi, V. Ciriani
{"title":"Autosymmetric Multiple-Valued Functions: Theory and Spectral Characterization","authors":"A. Bernasconi, V. Ciriani","doi":"10.1109/ISMVL.2011.13","DOIUrl":"https://doi.org/10.1109/ISMVL.2011.13","url":null,"abstract":"Auto symmetric functions are a class of Boolean functions whose regular structure can be exploited by synthesis algorithms in order to reduce the minimization time and to derive more compact algebraic forms. In this paper we propose a generalization of this class of functions to the multiple-valued logic framework. We also study the spectral properties of auto symmetric functions and provide a complete spectral characterization for both the Boolean and the multiple-valued setting.","PeriodicalId":234611,"journal":{"name":"2011 41st IEEE International Symposium on Multiple-Valued Logic","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123619598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A Comparison of Heterogeneous Multi-valued Decision Diagram Machines for Multiple-Output Logic Functions 多输出逻辑函数的异构多值决策图机的比较
2011 41st IEEE International Symposium on Multiple-Valued Logic Pub Date : 2011-05-23 DOI: 10.1109/ISMVL.2011.15
Hiroki Nakahara, Tsutomu Sasao, M. Matsuura
{"title":"A Comparison of Heterogeneous Multi-valued Decision Diagram Machines for Multiple-Output Logic Functions","authors":"Hiroki Nakahara, Tsutomu Sasao, M. Matsuura","doi":"10.1109/ISMVL.2011.15","DOIUrl":"https://doi.org/10.1109/ISMVL.2011.15","url":null,"abstract":"A heterogeneous multi-valued decision diagram~(HMDD) may have nodes with different numbers of variables. By partitioning the input variables into optimal disjoint sets, the HMDDs evaluate the function faster than BDDs with the same amount of memory. In this paper, we compare multi-output HMDD machines. First, we introduce three types of HMDDs: plural single-output HMDDs, Multi-Terminal HMDD, and HMDD for ECFN.Next, we show three HMDD machines~(HMDDMs). Then, we compare three HMDDMs with respect to the memory size, the execution time, and the area-time complexity. The comparison shows that, as for the area-time complexity, the HMDD for ECFN machine is the best.","PeriodicalId":234611,"journal":{"name":"2011 41st IEEE International Symposium on Multiple-Valued Logic","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125557364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
The Tensor PMV-algebra of an MV-algebra mv -代数的张量pmv -代数
2011 41st IEEE International Symposium on Multiple-Valued Logic Pub Date : 2011-05-23 DOI: 10.1109/ISMVL.2011.37
I. Leustean
{"title":"The Tensor PMV-algebra of an MV-algebra","authors":"I. Leustean","doi":"10.1109/ISMVL.2011.37","DOIUrl":"https://doi.org/10.1109/ISMVL.2011.37","url":null,"abstract":"The classical construction of tensor algebra is done in the context of MV-algebras. We construct the tensor PMV-algebra of an MV-algebra, which yields an adjunction between the category of MV-algebras and the category of PMV-algebras. In particular, for any MV-algebra A, the tensor PMV-algebra of A is the free PMV-algebra over A.","PeriodicalId":234611,"journal":{"name":"2011 41st IEEE International Symposium on Multiple-Valued Logic","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129927191","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Maximal Hyperclones Determined by Monotone Operations 由单调运算确定的最大超克隆
2011 41st IEEE International Symposium on Multiple-Valued Logic Pub Date : 2011-05-23 DOI: 10.1109/ISMVL.2011.46
Jelena Colic, Hajime Machida, J. Pantović
{"title":"Maximal Hyperclones Determined by Monotone Operations","authors":"Jelena Colic, Hajime Machida, J. Pantović","doi":"10.1109/ISMVL.2011.46","DOIUrl":"https://doi.org/10.1109/ISMVL.2011.46","url":null,"abstract":"Let A be a finite set. It is well known that every bounded partial order relation determines a maximal clone on A and every non-trivial partial order relation determines a maximal partial clone on A. In this paper we describe a class of maximal hyper clones that are determined by bounded partial order relations on A.","PeriodicalId":234611,"journal":{"name":"2011 41st IEEE International Symposium on Multiple-Valued Logic","volume":"2 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121008381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Classification of Ternary Logic Functions by Self-Dual Equivalence Classes 三元逻辑函数的自对偶等价类分类
2011 41st IEEE International Symposium on Multiple-Valued Logic Pub Date : 2011-05-23 DOI: 10.1109/ISMVL.2011.23
T. Soma, T. Soma
{"title":"Classification of Ternary Logic Functions by Self-Dual Equivalence Classes","authors":"T. Soma, T. Soma","doi":"10.1109/ISMVL.2011.23","DOIUrl":"https://doi.org/10.1109/ISMVL.2011.23","url":null,"abstract":"Self-dual equivalence class of ternary logic functions is investigated using ternary parametron logic. Based on multiplex or (MUX) realization of a function, a self-dual function is constructed by introducing Goto's self-dualizing variable which feeds constant values to MUX circuit. Self-dual operation is an operation to transform from one function to another among functions realized by different values of self-dualizing variable. It is defined as a combination of permutation group on values and positions of variables and that on values of function. It can be formulated as an exponentiation group by these groups and the equivalence class count is obtained from the cycle index of these groups.","PeriodicalId":234611,"journal":{"name":"2011 41st IEEE International Symposium on Multiple-Valued Logic","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116957491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Rev-Map: A Direct Gateway from Classical Irreversible Network to Reversible Network Rev-Map:从经典不可逆网络到可逆网络的直接网关
2011 41st IEEE International Symposium on Multiple-Valued Logic Pub Date : 2011-05-23 DOI: 10.1109/ISMVL.2011.38
S. Sultana, K. Radecka
{"title":"Rev-Map: A Direct Gateway from Classical Irreversible Network to Reversible Network","authors":"S. Sultana, K. Radecka","doi":"10.1109/ISMVL.2011.38","DOIUrl":"https://doi.org/10.1109/ISMVL.2011.38","url":null,"abstract":"We present an efficient way to realize reversible circuits directly from irreversible gate level descriptions, avoiding a search for reversible specifications of the original functions. In our scheme Toffoli-based implementation of classical gates can be used in topological order mapping. The method is then extended by introducing the notion of super cells, to reduce the number of extraneous bits and gate count. Our experimental results illustrate the impact of super cells on the size of the resulting reversible circuit. The results are better than previously proposed methods and BDD-based reversible synthesis approach.","PeriodicalId":234611,"journal":{"name":"2011 41st IEEE International Symposium on Multiple-Valued Logic","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129533973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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