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2011 41st IEEE International Symposium on Multiple-Valued Logic最新文献

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Design of a Low-Energy Nonvolatile Fully-Parallel Ternary CAM Using a Two-Level Segmented Match-Line Scheme 基于两级分段匹配线方案的低能量非易失性全并联三元凸轮设计
2011 41st IEEE International Symposium on Multiple-Valued Logic Pub Date : 2011-05-23 DOI: 10.1109/ISMVL.2011.41
S. Matsunaga, A. Katsumata, M. Natsui, T. Hanyu
{"title":"Design of a Low-Energy Nonvolatile Fully-Parallel Ternary CAM Using a Two-Level Segmented Match-Line Scheme","authors":"S. Matsunaga, A. Katsumata, M. Natsui, T. Hanyu","doi":"10.1109/ISMVL.2011.41","DOIUrl":"https://doi.org/10.1109/ISMVL.2011.41","url":null,"abstract":"A novel compact and static-power-free nonvolatile ternary content-addressable memory (TCAM) cell, where two-bit nonvolatile magnetic tunnel junction (MTJ) devices are stacked over the comparison logic circuit, is proposed for a high-density and ultra low-energy fully-parallel TCAM. The use of nonvolatile logic-in-memory circuit architecture makes it possible to realize 6T-2MTJ TCAM cell structure. The 144-bit word match-line is divided into two parts (first 10-bit and last 134-bit parts), which greatly reduces the dynamic power dissipation with small overhead of the switching delay. In fact, it is evaluated by the HSPICE simulation under a 90nm CMOS/MTJ technology that the search energy (power-delay product) of the proposed TCAM is reduced to 16 percent in comparison with that of a nonvolatile TCAM without using a segmented match-line scheme.","PeriodicalId":234611,"journal":{"name":"2011 41st IEEE International Symposium on Multiple-Valued Logic","volume":"17 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133481810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Time-Domain Multi-bit DeltaSigma Analog-to-Digital Converter 时域多位DeltaSigma模数转换器
2011 41st IEEE International Symposium on Multiple-Valued Logic Pub Date : 2011-05-23 DOI: 10.1109/ISMVL.2011.31
Kazuki Kuribayashi, K. Machida, Y. Toyama, T. Waho
{"title":"Time-Domain Multi-bit DeltaSigma Analog-to-Digital Converter","authors":"Kazuki Kuribayashi, K. Machida, Y. Toyama, T. Waho","doi":"10.1109/ISMVL.2011.31","DOIUrl":"https://doi.org/10.1109/ISMVL.2011.31","url":null,"abstract":"A multi-bit representation in the time domain has been applied to a DeltaSigma analog-to-digital converter (ADC), which consists of an asynchronous DeltaSigma  modulator (ADSM) and a time-to-digital converter (TDC). Current-mode circuits are included in the ADSM to suppress the variation in the node voltage. The TDC is based on a ring oscillator-based TDC comprised of four stages of differential delay element followed by a counter and a phase detector. The 1st-order noise-shaping was experimentally obtained for the TDC fabricated by using 0.18-µ m standard CMOS technology. A successful operation of the ADC has been obtained by transistor-level circuit simulation.","PeriodicalId":234611,"journal":{"name":"2011 41st IEEE International Symposium on Multiple-Valued Logic","volume":"240 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116232129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Speed-up of Neuromorphic Adiabatic Quantum Computation by Local Adiabatic Evolution 局部绝热进化加速神经形态绝热量子计算
2011 41st IEEE International Symposium on Multiple-Valued Logic Pub Date : 2011-05-23 DOI: 10.1109/ISMVL.2011.63
M. Kinjo, Katsuhiko Shimabukuro
{"title":"Speed-up of Neuromorphic Adiabatic Quantum Computation by Local Adiabatic Evolution","authors":"M. Kinjo, Katsuhiko Shimabukuro","doi":"10.1109/ISMVL.2011.63","DOIUrl":"https://doi.org/10.1109/ISMVL.2011.63","url":null,"abstract":"Farhi et al. have proposed an adiabatic quantum computation (AQC), which can be applied to NP-problems if one can know an appropriate Hamiltonian for a target problem. We have proposed a neuromorphic adiabatic quantum computation (NAQC) as the AQC with energy dissipation and an efficient method for designing a final Hamiltonian in consideration of the analogy with a neural network. The NAQC can be applied to optimization problems if its cost function can be expressed in a quadratic form. And successful operations have been confirmed by numerical simulations. In addition, local adiabatic evolution for quantum search have proposed by Roland et al. in order to speed-up the calculation time. In this paper, we show preliminary results for NAQC with local adiabatic evolution by numerical simulations.","PeriodicalId":234611,"journal":{"name":"2011 41st IEEE International Symposium on Multiple-Valued Logic","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122355421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Numeric Function Generators Using Piecewise Arithmetic Expressions 使用分段算术表达式的数值函数生成器
2011 41st IEEE International Symposium on Multiple-Valued Logic Pub Date : 2011-05-23 DOI: 10.1109/ISMVL.2011.32
Shinobu Nagayama, Tsutomu Sasao, J. T. Butler
{"title":"Numeric Function Generators Using Piecewise Arithmetic Expressions","authors":"Shinobu Nagayama, Tsutomu Sasao, J. T. Butler","doi":"10.1109/ISMVL.2011.32","DOIUrl":"https://doi.org/10.1109/ISMVL.2011.32","url":null,"abstract":"This paper proposes new architectures for numeric function generators (NFGs) using piecewise arithmetic expressions. The proposed architectures are programmable, and they realize a wide range of numeric functions. To designan NFG for a given function, we partition the domain of the function into uniform segments, and transform a sub-function in each segment into an arithmetic spectrum. From this arithmetic spectrum, we derive an arithmetic expression, and realize the arithmetic expression with hardware. Since the arithmetic spectrum has many zero coefficients and repeated coefficients, by storing only distinct nonzero coefficients in atable, we can significantly reduce the table size needed to store arithmetic coefficients. Experimental results show that the table size can be reduced to only a small percent of the table size needed to store all the arithmetic coefficients. We also propose techniques to reduce table size further and to improve performance.","PeriodicalId":234611,"journal":{"name":"2011 41st IEEE International Symposium on Multiple-Valued Logic","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127733735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Multiple-Valued Logic Networks with Regular Structure Obtained from Fast Fourier Transforms on Finite Groups 有限群上快速傅里叶变换得到正则结构的多值逻辑网络
2011 41st IEEE International Symposium on Multiple-Valued Logic Pub Date : 2011-05-23 DOI: 10.1109/ISMVL.2011.27
R. Stankovic, J. Astola, C. Moraga
{"title":"Multiple-Valued Logic Networks with Regular Structure Obtained from Fast Fourier Transforms on Finite Groups","authors":"R. Stankovic, J. Astola, C. Moraga","doi":"10.1109/ISMVL.2011.27","DOIUrl":"https://doi.org/10.1109/ISMVL.2011.27","url":null,"abstract":"In this paper, we discuss the Fast Fourier transform (FFT) on finite groups as a useful method in synthesis for regularity. FFT is the algorithm for efficient calculation of the Discrete Fourier transform (DFT) and has been extended to computation of various Fourier-like transforms. The algorithm has a very regular structure that can be easily mapped to technology by replacing nodes in the corresponding flow-graphs by circuit modules performing the operations in the flow-graphs. In this way, networks with highly regular structure for implementing functions from their spectra are derived. Fourier transforms on non-Abelian groups offer additional advantages for reducing the required hardware due to matrix-valued spectral coefficients and the way how such coefficients are used in reconstructing the functions. Methods for optimization of spectral representations of functions on finite groups may be applied to improve networks with regular structure.","PeriodicalId":234611,"journal":{"name":"2011 41st IEEE International Symposium on Multiple-Valued Logic","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129123913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Comparison of Influence of Two Data-Encoding Methods for Grover Algorithm on Quantum Costs Grover算法中两种数据编码方法对量子代价影响的比较
2011 41st IEEE International Symposium on Multiple-Valued Logic Pub Date : 2011-05-23 DOI: 10.1109/ISMVL.2011.29
S. Dhawan, M. Perkowski
{"title":"Comparison of Influence of Two Data-Encoding Methods for Grover Algorithm on Quantum Costs","authors":"S. Dhawan, M. Perkowski","doi":"10.1109/ISMVL.2011.29","DOIUrl":"https://doi.org/10.1109/ISMVL.2011.29","url":null,"abstract":"It is important to be able to calculate realistic estimates of quantum costs for real oracles used in quantum algorithms. In this paper, we compare Perkowski's[1] oracle data encoding method with Hogg's[2] encoding method for Grover algorithm[3], to examine the decrease in Oracle gate cost, if any, for four common constraint satisfaction problems: Graph coloring, Satisfiability, Send-More-Money and Max Clique.","PeriodicalId":234611,"journal":{"name":"2011 41st IEEE International Symposium on Multiple-Valued Logic","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130423170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Some Types of Filters in Hoops 一些类型的过滤器在箍
2011 41st IEEE International Symposium on Multiple-Valued Logic Pub Date : 2011-05-23 DOI: 10.1109/ISMVL.2011.9
M. Kondo
{"title":"Some Types of Filters in Hoops","authors":"M. Kondo","doi":"10.1109/ISMVL.2011.9","DOIUrl":"https://doi.org/10.1109/ISMVL.2011.9","url":null,"abstract":"In this paper we consider fundamental properties of some types of filters (implicative, positive implicative and fantastic filters) of hoops and prove that for any hoop $A$ and filter $F$ of $A$,begin{quote}(a) $F$ is an implicative filter if and only if $A/F$ is a relatively pseudo-complemented semi lattice, that is, Brouwerian semi lattice,(b) $F$ is a positive implicative filter if and only if $A/F$ is a ${wedge, vee, to, 1}$-reduct of Heyting algebra,(c) $F$ is a fantastic filter if and only if $A/F$ is a Wajsberg hoop.end{quote} Moreover we show that, for any filter of a hoop, it is a positive implicative filter if and only if it is an implicative and fantastic filter.","PeriodicalId":234611,"journal":{"name":"2011 41st IEEE International Symposium on Multiple-Valued Logic","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132088770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Note: Towards a Formalization of Guessing 注:走向猜测的形式化
2011 41st IEEE International Symposium on Multiple-Valued Logic Pub Date : 2011-05-23 DOI: 10.1109/ISMVL.2011.51
E. Trillas
{"title":"Note: Towards a Formalization of Guessing","authors":"E. Trillas","doi":"10.1109/ISMVL.2011.51","DOIUrl":"https://doi.org/10.1109/ISMVL.2011.51","url":null,"abstract":"A possible way towards the formalization and use of the conjecture concept, in such a way that logical consequences, hypotheses, and speculations, do be particular types of conjectures, is presented. It is shown that conjectures and hypotheses are anti-monotonic, but speculations are neither monotonic, nor anti-monotonic, that is, they are the only purely non-monotonic conjectures.","PeriodicalId":234611,"journal":{"name":"2011 41st IEEE International Symposium on Multiple-Valued Logic","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122341322","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
From Truth Tables to Programming Languages: Progress in the Design of Reversible Circuits 从真值表到编程语言:可逆电路设计的进展
2011 41st IEEE International Symposium on Multiple-Valued Logic Pub Date : 2011-05-23 DOI: 10.1109/ISMVL.2011.40
R. Drechsler, R. Wille
{"title":"From Truth Tables to Programming Languages: Progress in the Design of Reversible Circuits","authors":"R. Drechsler, R. Wille","doi":"10.1109/ISMVL.2011.40","DOIUrl":"https://doi.org/10.1109/ISMVL.2011.40","url":null,"abstract":"It is a widely supported prediction that conventional computer hardware technologies are going to reach their limits in the near future. Consequently, researchers are working on alternatives. Reversible circuits are one promising direction with applications e.g. in low-power design or quantum computation. However, no real design flow for this new kind of circuits exists so far. In this paper, the progress in the development of design methods for reversible circuits is reviewed -- with a particular focus on the synthesis steps. After a brief review on reversible circuits, the general idea of common synthesis approaches is described. This includes methods based on truth table descriptions, methods applicable to larger functions, and finally an approach based on a programming language. Discussions and an outlook to future work conclude this paper.","PeriodicalId":234611,"journal":{"name":"2011 41st IEEE International Symposium on Multiple-Valued Logic","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114611033","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 43
A Testable Realization for Decimal Multipliers 十进制乘数的可测试实现
2011 41st IEEE International Symposium on Multiple-Valued Logic Pub Date : 2011-05-23 DOI: 10.1109/ISMVL.2011.45
T. Hirayama, Y. Nishitani, S. Kitamura
{"title":"A Testable Realization for Decimal Multipliers","authors":"T. Hirayama, Y. Nishitani, S. Kitamura","doi":"10.1109/ISMVL.2011.45","DOIUrl":"https://doi.org/10.1109/ISMVL.2011.45","url":null,"abstract":"We propose a testable decimal multiplication circuit under the single cell fault model. The multiplier consists of iterative logic arrays of partial product generators and adders. We also give a set of test patterns to detect single faults in the circuit. The number of test patterns is proportional to that of the input digits of the multiplier, which is significantly smaller than the exponential number of test patterns required in non-testable circuits. This efficient testability is achieved only by as light change of the function in the partial product generators and an insertion of some testing inputs in the adders. No additional hardware modules are required in the proposed realization.","PeriodicalId":234611,"journal":{"name":"2011 41st IEEE International Symposium on Multiple-Valued Logic","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125634876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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