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2011 41st IEEE International Symposium on Multiple-Valued Logic最新文献

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Index Generation Functions: Recent Developments 索引生成函数:最近的发展
2011 41st IEEE International Symposium on Multiple-Valued Logic Pub Date : 2011-05-23 DOI: 10.1109/ISMVL.2011.17
Tsutomu Sasao
{"title":"Index Generation Functions: Recent Developments","authors":"Tsutomu Sasao","doi":"10.1109/ISMVL.2011.17","DOIUrl":"https://doi.org/10.1109/ISMVL.2011.17","url":null,"abstract":"This survey first introduces index generation functions, which are useful for pattern matching in communication circuits. Then, it shows various methods to realize index generation functions using memories. A linear transformation is used to reduce the number of variables and thus memory size. An extension to the multiple-valued case is also presented.","PeriodicalId":234611,"journal":{"name":"2011 41st IEEE International Symposium on Multiple-Valued Logic","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123050191","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 36
Two-Qubit Quantum Gates to Reduce the Quantum Cost of Reversible Circuit 降低可逆电路量子成本的双量子位量子门
2011 41st IEEE International Symposium on Multiple-Valued Logic Pub Date : 2011-05-23 DOI: 10.1109/ISMVL.2011.56
M. Rahman, A. Banerjee, G. Dueck, A. Pathak
{"title":"Two-Qubit Quantum Gates to Reduce the Quantum Cost of Reversible Circuit","authors":"M. Rahman, A. Banerjee, G. Dueck, A. Pathak","doi":"10.1109/ISMVL.2011.56","DOIUrl":"https://doi.org/10.1109/ISMVL.2011.56","url":null,"abstract":"This paper presents a quantum gate library that consists of all possible two-qubit quantum gates which do not produce entangled states. The quantum cost of each two-qubit gate in the proposed library is one. Therefore, these gates can be used to reduce the quantum costs of reversible circuits. Experimental results show a significant reduction of quantum cost in benchmark circuits. The resulting circuits could be further optimized with existing tools, such as quantum template matching.","PeriodicalId":234611,"journal":{"name":"2011 41st IEEE International Symposium on Multiple-Valued Logic","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127152882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
On the Skipped Variables of Quantum Multiple-Valued Decision Diagrams 论量子多值决策图的跳过变量
2011 41st IEEE International Symposium on Multiple-Valued Logic Pub Date : 2011-05-23 DOI: 10.1109/ISMVL.2011.22
D. Y. Feinstein, M. Thornton
{"title":"On the Skipped Variables of Quantum Multiple-Valued Decision Diagrams","authors":"D. Y. Feinstein, M. Thornton","doi":"10.1109/ISMVL.2011.22","DOIUrl":"https://doi.org/10.1109/ISMVL.2011.22","url":null,"abstract":"The data structure referred to as quantum multiple-valued decision diagrams (QMDD) is used to efficiently represent the unitary matrices describing reversible and quantum circuits. This paper investigates the conditions that cause skipped variables to appear in the QMDD of some binary and ternary quantum circuits. We have found that a unitary matrix that produces a skipped variable in a QMDD is likely to cause a specific anomaly when it is decomposed into a cascade of two-level unitary matrices by the Beck-Zeilinger-Bernstein-Bertani algorithm.","PeriodicalId":234611,"journal":{"name":"2011 41st IEEE International Symposium on Multiple-Valued Logic","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125552024","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A Graph-Based Approach to Designing Multiple-Valued Arithmetic Algorithms 基于图的多值算术算法设计方法
2011 41st IEEE International Symposium on Multiple-Valued Logic Pub Date : 2011-05-23 DOI: 10.1109/ISMVL.2011.44
Kazuya Saito, N. Homma, T. Aoki
{"title":"A Graph-Based Approach to Designing Multiple-Valued Arithmetic Algorithms","authors":"Kazuya Saito, N. Homma, T. Aoki","doi":"10.1109/ISMVL.2011.44","DOIUrl":"https://doi.org/10.1109/ISMVL.2011.44","url":null,"abstract":"This paper presents a graph-based approach to designing multiple-valued arithmetic circuits. Our method describes arithmetic circuits in a hierarchical manner with high-level multiple-valued graphs, which are determined by specific algebra and arithmetic formulae. The proposed circuit description can be effectively verified by symbolic computations such as polynomial reduction using Groebner Bases. In this paper, we describe the proposed graph representation and show an example of its description and verification. The advantageous effects of the proposed approach are demonstrated through experimental designs of parallel multipliers over Galois field GF(2^m) for different word-lengths and irreducible polynomials. The result shows that the proposed approach has a definite possibility of verifying practical arithmetic circuits where the conventional simulation techniques failed.","PeriodicalId":234611,"journal":{"name":"2011 41st IEEE International Symposium on Multiple-Valued Logic","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115203286","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Answer Set Programming: A Declarative Approach to Solving Challenging Search Problems 答案集编程:解决具有挑战性的搜索问题的声明式方法
2011 41st IEEE International Symposium on Multiple-Valued Logic Pub Date : 2011-05-23 DOI: 10.1109/ISMVL.2011.61
I. Niemelä
{"title":"Answer Set Programming: A Declarative Approach to Solving Challenging Search Problems","authors":"I. Niemelä","doi":"10.1109/ISMVL.2011.61","DOIUrl":"https://doi.org/10.1109/ISMVL.2011.61","url":null,"abstract":"Answer Set Programming (ASP) is a declarative programming paradigm targeted to solving search problems. The basic idea of ASP is similar to, for example, SAT-based planning or constraint satisfaction problems but ASP provides a more powerful knowledge representation language for effective problem encoding. A number of successful ASP systems have already been developed and applied in a large range of areas. The talk explains the theoretical underpinnings of ASP, introduces the answer set programming paradigm, outlines computational techniques used in current ASP solvers, and discusses some interesting applications of the approach.","PeriodicalId":234611,"journal":{"name":"2011 41st IEEE International Symposium on Multiple-Valued Logic","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129500070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Complementary Multiple-Valued Encoding Scheme for Interconnect-Fault-Resilient Bidirectional Asynchronous Links 双向异步链路的互补性多值编码方案
2011 41st IEEE International Symposium on Multiple-Valued Logic Pub Date : 2011-05-23 DOI: 10.1109/ISMVL.2011.30
Atsushi Matsumoto, N. Onizawa, T. Hanyu
{"title":"Complementary Multiple-Valued Encoding Scheme for Interconnect-Fault-Resilient Bidirectional Asynchronous Links","authors":"Atsushi Matsumoto, N. Onizawa, T. Hanyu","doi":"10.1109/ISMVL.2011.30","DOIUrl":"https://doi.org/10.1109/ISMVL.2011.30","url":null,"abstract":"In this paper, we propose a new encoding scheme for multiple-valued dual-rail data representation in asynchronous links with open-wire fault. Since data-arrival state is detected by the summation of the current signal, error states which are caused by the open-wire fault can be distinguished from the correct states by using proposed textit{Complementary Encoding}. Detection of these error states makes it possible to maintain the transmission capability of the links. The open-wire fault detect ability by using proposed encoding-based data representation is mathematically proven in this paper. And a simple example of data representation based on the proposed encoding scheme is also demonstrated.","PeriodicalId":234611,"journal":{"name":"2011 41st IEEE International Symposium on Multiple-Valued Logic","volume":"73 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128412178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Maximal Centralizing Monoids and their Relation to Minimal Clones 极大中心化一元群及其与极小克隆的关系
2011 41st IEEE International Symposium on Multiple-Valued Logic Pub Date : 2011-05-23 DOI: 10.1109/ISMVL.2011.36
Hajime Machida, I. Rosenberg
{"title":"Maximal Centralizing Monoids and their Relation to Minimal Clones","authors":"Hajime Machida, I. Rosenberg","doi":"10.1109/ISMVL.2011.36","DOIUrl":"https://doi.org/10.1109/ISMVL.2011.36","url":null,"abstract":"A centralizing monoid is a set of unary functions on a fixed set $A$ which commute with some set of functions on $A$. It is known to be hard to determine effectively such centralizing monoids. In this paper we focus on maximal centralizing monoids. It is proved that they have strong connection to minimal clones. We determine all maximal centralizing monoids on a three-element set and, then, prove a general result relating constant functions to maximal centralizing monoids.","PeriodicalId":234611,"journal":{"name":"2011 41st IEEE International Symposium on Multiple-Valued Logic","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126322226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Some Basic Ternary Operations Using Toffoli Gates Along with the Cost of Implementation 一些使用Toffoli门的基本三元运算及其实现成本
2011 41st IEEE International Symposium on Multiple-Valued Logic Pub Date : 2011-05-23 DOI: 10.1109/ISMVL.2011.34
A. Biswas, S. Chowdhury, Md. Mahmud Muntakim Khan, M. Hasan, A. Khan
{"title":"Some Basic Ternary Operations Using Toffoli Gates Along with the Cost of Implementation","authors":"A. Biswas, S. Chowdhury, Md. Mahmud Muntakim Khan, M. Hasan, A. Khan","doi":"10.1109/ISMVL.2011.34","DOIUrl":"https://doi.org/10.1109/ISMVL.2011.34","url":null,"abstract":"We realize square operation for quantum ternary logic using basic quantum ternary gates. With the aid of this square operation, we develop a square-multiplier unit. We further develop a cost measurement technique of the square operation and square multiplication operation through general expressions.","PeriodicalId":234611,"journal":{"name":"2011 41st IEEE International Symposium on Multiple-Valued Logic","volume":"79 10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130280992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A Realization Method of Forward Converters from Multiple-Precision Binary Numbers to Residue Numbers with Arbitrary Mutable Modulus 一种从多精度二进制数到任意变模残数的前向转换器的实现方法
2011 41st IEEE International Symposium on Multiple-Valued Logic Pub Date : 2011-05-23 DOI: 10.1109/ISMVL.2011.48
Koki Shirakawa, Takashi Uemura, Y. Iguchi
{"title":"A Realization Method of Forward Converters from Multiple-Precision Binary Numbers to Residue Numbers with Arbitrary Mutable Modulus","authors":"Koki Shirakawa, Takashi Uemura, Y. Iguchi","doi":"10.1109/ISMVL.2011.48","DOIUrl":"https://doi.org/10.1109/ISMVL.2011.48","url":null,"abstract":"This paper presents a realization method of forward converters from multiple-precision binary numbers to residue numbers. Single-precision forward converters use conversion tables realized with memories. However, multiple-precision, e.g. more than 1024 bits, forward converters require huge memories. This paper proposes the circuit calculating a value in the conversion table in every clock cycle. Experimental results show that the proposed method can quadruplicate the dynamic range.","PeriodicalId":234611,"journal":{"name":"2011 41st IEEE International Symposium on Multiple-Valued Logic","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134240849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design of High Performance Quaternary Adders 高性能四元加法器的设计
2011 41st IEEE International Symposium on Multiple-Valued Logic Pub Date : 2011-05-23 DOI: 10.1109/ISMVL.2011.65
K. V. Patel, K. Gurumurthy
{"title":"Design of High Performance Quaternary Adders","authors":"K. V. Patel, K. Gurumurthy","doi":"10.1109/ISMVL.2011.65","DOIUrl":"https://doi.org/10.1109/ISMVL.2011.65","url":null,"abstract":"Design of the binary logic circuits is limited by the requirement of the interconnections. A possible solution could be arrived at by using a larger set of signals over the same chip area. Multiple-valued logic (MVL) designs are gaining importance from that perspective. This paper presents two types of multiple-valued full adder circuits, implemented in Multiple-Valued voltage-Mode Logic (MV-VML). First type is designed using one hot encoding and barrel shifter. Second full adder circuit is designed by converting the quaternary logic in to unique code, which enables to implement circuit with reduced hard ware. Sum and carry are processed in two separate blocks, controlled by code generator unit. The design is targeted for the 0.18 µm CMOS technology and verification of the design is done through Synopsis HSPICE and COSMOSCOPE Tools. Area of the designed circuits is less than the corresponding binary circuits and quaternary adders because number of transistors used are less.","PeriodicalId":234611,"journal":{"name":"2011 41st IEEE International Symposium on Multiple-Valued Logic","volume":"37 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129763735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 35
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