基于浮门和多值逻辑的超低压高速CMOS全加法器

2011 41st IEEE International Symposium on Multiple-Valued Logic Pub Date : 2011-05-23 DOI:10.1109/ISMVL.2011.11

Y. Berg

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引用次数: 2

摘要

本文提出了一种基于超低压半浮栅CMOS逻辑的高速超低压全加法器电路。全加法器电路包含一个高速超低压载流发生器电路和一个多值求和的中间表示。全加法器适用于低压串行全加法器设计。所提出的模拟数据适用于90nm台积电CMOS工艺。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Ultra Low-Voltage and High-Speed CMOS Full Adder Using Floating-Gates and Multiple-Valued Logic

In this paper we present a novel high speed and ultra low-voltage full adder circuit based on ultra low-voltage semi floating-gate CMOS logic. The full adder circuit contains a high speed ultraslow-voltage carry generator circuit and a multiple-valued intermediate representation of the summation. The full adder is suitable for low-voltage serial full adder design. Simulated data presented is valid for a 90nm TSMC CMOS process.

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2011 41st IEEE International Symposium on Multiple-Valued Logic

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