Information-Preserving Logic Based on Logical Reversibility to Reduce the Memory Data Transfer Bottleneck and Heat Dissipation

Abstract

We present an approach to the cache bottleneck problem using reversible logic circuits. The high traffic between the cache and the main memory in current systems considerably slows down the performance of the general information processing unit (IPU). Moreover this high traffic has the consequence of high heat generation in VLSI elements such as the CPU or dedicated processors. Thus the reduction in use or complete removal of the cache memory could be beneficial to current processors architecture. We present a model where the IPU is designed as a logically reversible circuit. This allows one to reduce the cachememory traffic because data can be recovered using the output of the current processing. We illustrate the implementation of the approach by providing a design of an adiabatic reversible Toffoli gate with a power consumption equivalent to a classical adiabatic circuit. With these approaches, the cache-memory bottleneck and heat dissipation can potentially be reduced even by using only logically reversible circuit implementation.