2005 6th International Conference on Electronic Packaging Technology最新文献

{"title":"Board Level FBGA Package Combined Thermal Cycling & Bending Fatigue Study","authors":"Hui Wang, Jianwei Zhou, Taekoo Lee, Jun Wang, F. Xiao","doi":"10.1109/ICEPT.2005.1564672","DOIUrl":"https://doi.org/10.1109/ICEPT.2005.1564672","url":null,"abstract":"A combined thermal cycling and bending fatigue test method is proposed for board level FBGA package. The fatigue lifetime of the board level FBGA package is studied with the combined acceleration method both with experimental and numerical analysis. The influence of initial pre-temperature cycling treatment on the bending fatigue life is studied. The failure analysis of failed samples was conducted, cracks were found in different sites of the package. The numerical analysis of the combined temperature cycle test and bending test was conducted. The simulation results of fatigue lifetime and failure site correspond to the experiment result well","PeriodicalId":234537,"journal":{"name":"2005 6th International Conference on Electronic Packaging Technology","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128610867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Surface activation process of lead-free solder bumps for low temperature bonding","authors":"Yinghui Wang, K. Nishida, M. Hutter, M. Howlader, E. Higurashi, T. Suga, T. Kimura","doi":"10.1109/ICEPT.2005.1564688","DOIUrl":"https://doi.org/10.1109/ICEPT.2005.1564688","url":null,"abstract":"Focused on the problems of the lead-free alloys bonding at high melting temperature, high density, low cost and low temperature lead-free flip chip bonding process was developed by the surface activated bonding (SAB) method. Sn-3.0Ag-0.5Cu (wt %) alloy, with better reliability and solderability than other alternatives for electronic packaging, were chose for the experiments to be bonded with typical electrodes, SnAg, Cu and Au film. The feasibility of Sn-3.0Ag-0.5Cu SAB bonding at room temperature was confirmed. The bonding strength in vacuum and N/sub 2/ was high. In air, it was found that the bonding strength was highly depended on exposure time. Combined with low temperature (150/spl deg/C), SAB bonding process was developed in air by using 30 /spl mu/m pitch Au/Sn flip chip samples for the first time. Resistance and tensile test showed good electrical and mechanical properties of the bonded Au/Sn samples. Bonding interfaces were observed by scanning electron microscope (SEM) and electron probe microanalyzer (EPMA).","PeriodicalId":234537,"journal":{"name":"2005 6th International Conference on Electronic Packaging Technology","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116743316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A novel Z-axis capacitive accelerometer using-SOG structure","authors":"C. Weiping, Huo Mingxue, Lin Yumin, L. Xiaowei, Zhang Ruichao","doi":"10.1109/ICEPT.2005.1564703","DOIUrl":"https://doi.org/10.1109/ICEPT.2005.1564703","url":null,"abstract":"A differential capacitive silicon z-axis micro-accelerometer using SOG (silicon on glass) structure, based on bulk micromachining technology is proposed and a novel structure is designed. The device with a three-layer structure can provide a variable sensitivity as changing the thickness of the beam fabricated, by only one set of masks. The simulation of the static and modal performance of the accelerometer structure is completed with the FEM (finite element method) and the optimized design of the accelerometer is accomplished. The key techniques in the fabrication are investigated and the process flow is designed, furthermore, corner compensation structure was used in the masks to avoid convex corner undercutting, which is simulated and optimized by process simulation (IntelliSuite). The mechanical sensitivity of the accelerometer varies from 2.37/spl times/10/sup -7//w/g/sub n/ to 1.74 /spl times/10/sup -/8m/g/sub n/ as the thickness of the beam from 50/spl mu/m to 20/spl mu/m.","PeriodicalId":234537,"journal":{"name":"2005 6th International Conference on Electronic Packaging Technology","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121786723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Additives effects on growth pattern modification of Cu6Sn5-based intermetallic compounds during reflow process","authors":"F. Gao, T. Takemoto","doi":"10.1109/ICEPT.2005.1564695","DOIUrl":"https://doi.org/10.1109/ICEPT.2005.1564695","url":null,"abstract":"The growth pattern of intermetallic compounds generated between Cu substrate and the eutectic Sn-3.5Ag doped with small amount of additives (0.1 mass%), say, Ni or Co, was explored in this paper. During reflow experiments, the dwell time at peak temperature 250 °C was set up for 1, 2, 5, 10, 20, 30 and 60seconds respectively to investigate the intermetallic morphology growth behavior. The intermetallics formed between Cu substrate and three kinds of solders, namely, Sn-3.5Ag, Sn-3.5Ag-0.1Co and Sn-3.5Ag-0.1Ni, were all identified as Cu6Sn5-based, although the additives participated in the interfacial reaction. However, the rounded shape of Cu6Sn5 was observed, while the (Cu, Ni) 6Sn5 or (Cu, Co) 6Sn5 intermetallics were polyhedral shaped (or faceted). The presence of additives (Ni or Co) at the outer region of (Cu, Ni) 6Sn5 or (Cu, Co) 6Sn5 IMCs was responsible for the morphology transit, which might lead to the increase of enthalpy change and thus result in the Jackson’s parameter larger than 2. Another attractive result was the evolution of grain size distribution. For the grains of typical Cu6Sn5 intermetallic, the size distribution tended to be more narrow following with the extended reflow time, although the number of intermetallic was reduced. However, for the (Cu, Ni) 6Sn5 or (Cu, Co) 6Sn5 intermetallics, the grain size distribution became wider and spread out.","PeriodicalId":234537,"journal":{"name":"2005 6th International Conference on Electronic Packaging Technology","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126544217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thick Film Lithography Techniques utilizing state-of-the-art Proximity Aligners for BEoL Applications","authors":"R. Pelzer, H. Kirchberger","doi":"10.1109/ICEPT.2005.1564705","DOIUrl":"https://doi.org/10.1109/ICEPT.2005.1564705","url":null,"abstract":"Wafer-level packaging is a promising technology to meet future demands of increased performance for advanced integrated circuits with tighter pitch and higher I/O counts (higher feature density). Innovative equipment technology for new full field lithography techniques is at the forefront of the technology roadmap and perfectly suited for wafer-level packaging, including bond-bad redistribution and fine pitch wafer bumping applications. Typically advanced packaging applications involve thick resist processing of films in the range of up to 100mum, exposure of conformal films on topography and the requirement for steep, controllable sidewall angles. The smallest required resolutions are in the range of 20mum in thick film photoresists for bumping applications and 3-5mum for pad redistribution lines in dielectric resins, like BCB. The alignment and exposure requirements for the lithographic process in WLP will be discussed. Projection aligners are still the first choice for WLP, even if the investments are much higher compared to the 1times proximity aligner. We will demonstrate that state-of-the-art proximity aligner fulfil all requirements for WLP and embedded passives","PeriodicalId":234537,"journal":{"name":"2005 6th International Conference on Electronic Packaging Technology","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125257448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The diffusion of Ni into Al wire at the interface of ultrasonic wire bond during high temperature storage","authors":"H. Ji, Mingyu Li, Au Tai Kung, Chunqing Wang, Dongqing Li","doi":"10.1109/ICEPT.2005.1564652","DOIUrl":"https://doi.org/10.1109/ICEPT.2005.1564652","url":null,"abstract":"Ultrasonic wire bonding is one of the most important techniques for die interconnection in microelectronic packaging. It is widely used for power devices, microwave devices and photoelectron devices packaging. At room temperature, ultrasonic energy and plastic deformation energy, generated by metal wire plastic deformation under the wedge tool pressure, make the wire and metallization join together. The ultrasonic bonds, after bonding and aging, of Al+1%Si wire with 25/spl mu/m diameter bonded on the Au/Ni/Cu pad, are analyzed by scanning electronic microscopy (SEM) with energy dispersive x-ray spectrometer (EDX). The joints begin at the bond periphery where it is the location of the greatest plastic flow. It is found that the mechanism of ultrasonic bonding is, both the plastic flow of metal wire generated by wedge tool pressure which results in the diffusion of Ni into Al wire; and the effect of ultrasound is that, on the one hand, ultrasonic vibration enhances the metal wire ability of plastic flow and, on the other hand, it generates many defects inside the metal wire which are the fast diffusion channels. The diffusion type is likely the short-circuit diffusion, which is more prominent than the crystal diffusion when the temperature is low. After high temperature storage at 170 /spl deg/C for 10 days, there is evident diffusion of Ni into Al wire, but the microstructure is the same with the bonds after bonding, there is no evident change. Aged for 30 days, the bond interface forms a cloud-like structure, and the major composition is Al and Ni with weight percent of 78.82% and 15.55% respectively. However, the diffusion is not even and some parts of the bond interface are absence of Ni diffusion. When the aging time is 40 days, the cloud-like structure transforms into rectangular island-like structure and there are many cavities inside the bond wire, which are different from the Kirkendall voids because of the shape and dimension.","PeriodicalId":234537,"journal":{"name":"2005 6th International Conference on Electronic Packaging Technology","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133276824","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Reliability enhancement of wafer level packaging using solder ball layout methodology","authors":"Chang-Ming Liu, K. Chiang","doi":"10.1109/ICEPT.2005.1564738","DOIUrl":"https://doi.org/10.1109/ICEPT.2005.1564738","url":null,"abstract":"In the design and manufacturing process of electric packaging, solder joint are generated with a variety of methods to provide both mechanical and electrical connection for applications such as flip chip, wafer level packaging, fine pitch ball grid array (BGA), and chip scale packaging (CSP). Solder joint shape prediction method has been incorporated as a design tool to enhance the reliability of the wafer level packaging. Wafer level chip-scale-packaging (WLCSP) is expected to be widely used in static-dynamic random access memory (SDRAM) for its higher electrical performance and lower manufacturing costs. However, reliability of solder joints for large chip size such as 6mm /spl times/ 6mm without underfill assembly is still in question. In conventional WLCSP, the dimension of each solder ball and each solder pad is the same. The maximum thermally induced stress/strain would occur on the die-side surface of the solder joint that are located farthest away the chip center. In this research, a hybrid method combined analytical algorithm and energy-based method is applied to predict standoff heights and geometry profiles of solder balls. A hybrid-pad-shape (HPS) system is also proposed to design solder ball layout and to enhance the reliability of solder joints. The HPS system contains two kinds of solder volume and pad diameters as well as their relative location during reflow process. Next, a commercial finite element code ANSYS is applied to simulate the stress/strain behavior of the solder balls in WLCSP under temperature cycling conditions. In addition, a nonlinear and parametric finite element analysis is conducted to investigate the reliability issues that result from several design parameters including solder joint layout, solder volume, pad diameter, die/substrate thickness, and thickness/material properties of stress buffer layer (SBL). The results reveal that as the WLCSP contains larger solder balls located at corner area underneath the chip, the maximum equivalent plastic strain of the solder joints would be evidently reduced and the solder joint reliability under thermal loading would be highly enhanced. On the other hand, thinner die and thicker SBL are also good for the reliability of the WLCSP. Furthermore, the findings presented in this research can be used as a design guideline for area array interconnections such as CSP, flip chip packaging, super CSP and fine pitch BGA.","PeriodicalId":234537,"journal":{"name":"2005 6th International Conference on Electronic Packaging Technology","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115094612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Nano-silver paste with low roasting temperature","authors":"Xiuyu Wang, Zhisheng Zhang","doi":"10.1109/ICEPT.2005.1564619","DOIUrl":"https://doi.org/10.1109/ICEPT.2005.1564619","url":null,"abstract":"A kind of new silver paste with silver content about 50wt%, nano-silver paste, significantly different with normal silver paste in roasting temperature, was prepared using nano-silver powder, ethanol, n-butyl alcohol, n-hexyl alcohol and low polymer fibre. The nano-silver paste shows weight loss and volatilization with different levels on thermogravimetric (TG) analyzing curve. Field emission scanning electron microscope (FESEM) analysis indicates when roasting temperature is controlled at 200/spl deg/C, the surface of finished silver film has already been compact and smooth. And finished silver film has stronger adhesive with ceramic and mental substrates, while the adhesive is poor with slippery glass. The minimal square resistor of obtained silver film can reach 7.8m/spl Omega///spl square/.","PeriodicalId":234537,"journal":{"name":"2005 6th International Conference on Electronic Packaging Technology","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114062323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Transient Behaviors of A High Temperature SOI Based Pressure Sensor","authors":"Xiaojun Wang, R. Guan, Zhiyan Gan, Sheng Liu","doi":"10.1109/ICEPT.2005.1564702","DOIUrl":"https://doi.org/10.1109/ICEPT.2005.1564702","url":null,"abstract":"Silicon on insulator (SOI) is becoming a more favorable technology to make membrane in MEMS as compared to traditional poly-silicon due to its high temperature capability and more uniformity in controlling its geometry. In our study, a high temperature pressure sensor is designed based on a SOI based MEMS chip bonded on the cantilever beam. A unique structure is designed to shelter the thermal shock which could occur in testing and operation. In our modeling, transient thermo-mechanical modeling is conducted. A thermal shock with the maximum temperature of 2000degC is applied to exposed areas of the packaging structure, and the maximum temperature could keep steady for 1500ms during the thermal shock. Detailed temperature field as a function of time is provided on the chip, which shows that the chip temperature is well below the required specification which is on the level of within 500ms. In addition, the deformation and stress of the packaging structure with various packaging bonding materials are also provided by our models. For this packaging structure, the selection of the bonding materials is an important factor during the packaging design process. The performance, such as the linearity, range and life-time, for the packaging structure of the pressure sensor is also limited by the CTE (coefficient of temperature expansion), Young's modulus, and thermal conductivity of bonding materials which all are considered in the selection of bonding materials. The packaging structure with relatively soft bonding materials shows uniform deformation among the piezo-resistive areas, while the strain and stress distribution of the packaging structure also could obtain the optimization in operation","PeriodicalId":234537,"journal":{"name":"2005 6th International Conference on Electronic Packaging Technology","volume":"90 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120984430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A MCM Interconnect Test Generation Optimization Scheme Based on Ant Algorithm and Genetic Algorithm","authors":"Chen Lei","doi":"10.1109/ICEPT.2005.1564674","DOIUrl":"https://doi.org/10.1109/ICEPT.2005.1564674","url":null,"abstract":"The paper presents a hybrid optimization scheme of ant algorithm (AA) and genetic algorithm (GA) for the interconnect test generation problem in multi-chip module (MCM). In this scheme, the AA is employed to generate the initial candidate vectors for the MCM interconnect test generation, where the pheromone updating rule and state transition rule of AA is designed. Then the GA evolves the candidate vectors generated by AA, using a fault simulator to evaluate the fitness of each candidate vector. Various GA parameters are investigated, including selection operator, crossover operator, crossover and mutation rate, as well as number of generation and population size. The international standard MCM circuit was used to verify the scheme. The results indicate that the performance of the scheme in execution time and fault coverage is comparable to other deterministic algorithms","PeriodicalId":234537,"journal":{"name":"2005 6th International Conference on Electronic Packaging Technology","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124620420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}