2005 6th International Conference on Electronic Packaging Technology最新文献

{"title":"Plasma considerations prior to wire bonding in advanced packaging","authors":"J. Zhao, J. Getty","doi":"10.1109/ICEPT.2005.1564616","DOIUrl":"https://doi.org/10.1109/ICEPT.2005.1564616","url":null,"abstract":"Today's packaging engineers are faced with many challenges, including cost-saving strategies, yield-enhancing process steps, and damage-free preparation of intricate, small geometry devices such as multi-chip modules, stacked packages and hybrids. In order to ensure high device reliability and minimize manufacturing costs, a well-prepared surface for wire bonding plays a very important role in successful advanced packaging since it can significantly improve the quality and reliability of the bond. Gas plasma technology can be used to clean pads prior to wire bonding to improve bond strengths and yields. It is a powerful, efficient resource for surface preparation that can dramatically improve the manufacturability, reliability, and yield of advanced packages. In this paper, the types of plasma technologies and consideration for their use prior to wire bonding are discussed, and experimental results are reviewed. Examples specific to epoxy bleed-out contamination and considerations regarding substrate material and device characteristics are also addressed.","PeriodicalId":234537,"journal":{"name":"2005 6th International Conference on Electronic Packaging Technology","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132595443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Microstructure and Mechanical Properties Investigation of Lead-free Solder Sn99.3Cu0.7","authors":"F. Zhu, Honghai Zhang, R. Guan, Sheng Liu","doi":"10.1109/ICEPT.2005.1564686","DOIUrl":"https://doi.org/10.1109/ICEPT.2005.1564686","url":null,"abstract":"In the late years, environment concerns have attracted more and more attention in many countries, because of pollution from the lead-based solders and its compounds. Many countries are about to ban using of lead-based solders in microelectronic packaging; the lead-free solders will replace the tin-lead (Sn-Pb) eutectic solders. Due to higher melting temperature of most candidate lead-free solders, however, mechanical properties of them have not been available and are poorly understood. Failure of microelectronic components is mostly likely due to the inferior mechanical properties of solder alloys used in microelectronic components packaging and interconnecting. In this study, microstructure and mechanical properties of lead-free solder alloy Sn 99.3Cu0.7 (Ni) are investigated. The paper will compare the mechanical properties of the lead-based and lead-free solder alloys (Sn99.3Cu0.7 (Ni) and 63Sn37Pb). The tensile test of lead-based and lead-free solder alloys (Sn99.3Cu0.7(Ni) and Sn63Pb37) was conducted at room and elevated temperatures; the relevant tensile properties of them were obtained in this paper. Specifically, the tensile strength of this lead-free solder - Sn99.3Cu0.7 (Ni) in 25degC, 50degC, 75degC, 100degC, 125degC was obtained; and it was found that tensile strength of the lead-free solder decreases with increasing test temperature at constant strain rate. The lead-free solder alloy Sn 99.3Cu0.7 (Ni) was found to have favorable mechanical properties and it may be able to replace the lead-based solder alloy such as Sn63Pb37","PeriodicalId":234537,"journal":{"name":"2005 6th International Conference on Electronic Packaging Technology","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133821712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Strength Reliability for Surfaces micro-machined Polycrystalline silicon Micro-Cantilevers","authors":"Jiang Li-li, Tang Jie-ying","doi":"10.1109/ICEPT.2005.1564631","DOIUrl":"https://doi.org/10.1109/ICEPT.2005.1564631","url":null,"abstract":"MEMS components failure often happens where environment effects, such as shock, vibration, and temperature cycles. In this paper, the reliability of surfaces micro-machined polycrystalline silicon micro-cantilevers under shock loads was discussed. Using interference theory of stress and strength in the mechanical field, the reliability model was presented and it can predict the probability of the reliability of the cantilever under shock loads. It will help improve the design of MEMS","PeriodicalId":234537,"journal":{"name":"2005 6th International Conference on Electronic Packaging Technology","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123873258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Lead-free solders based on the Sn-8Zn-3Bi ternary alloy with additions of In, Nd or La","authors":"Yangshan Sun, F. Xue, Jian Zhou","doi":"10.1109/ICEPT.2005.1564670","DOIUrl":"https://doi.org/10.1109/ICEPT.2005.1564670","url":null,"abstract":"The Sn-8Zn-3Bi alloy is a new lead-free solder designed for possible replacement of Sn-Pb solders for its low melting temperature and low cost, but wettability and oxidation resistance of the alloy are unsatisfactory. This paper demonstrates the effect of the fourth additive (In, La, Nd) on properties of Sn-8Zn-3Bi solders including wetting behavior, oxidation resistance, melting behavior and mechanical properties. Wetting balance method was used to measure wetting force and wetting time on Cu substrate of the Sn-8Zn-3Bi-X solders. The results show that In, Nd and La are the effective additive elements on increasing the wetting force and shortening the wetting time, when In addition was 0.2/spl sim/1.0wt%, and the rare earth element (La or Nd) addition was 0.03/spl sim/0.2wt%. The oxidation behavior was examined by a thermo-gravimetric analyzer (TGA) for solder powders. In or Nd addition obviously decreased the weight of the oxides formed at the surface of the solder. Auger electron spectra (AES) analysis was applied to determine the identity of the oxides. The results indicate that besides ZnO, La/sub 2/O/sub 3/ or Nd/sub 2/O/sub 3/ formed at the surface of the rare earth contained solders. But there was no other oxide except ZnO existed at the surface of In contained Sn-8Zn-3Bi solders. Thermal analysis for the solders was performed by differential scanning calorimetry (DSC). According to DSC profiles for the Sn-8Zn-3Bi containing rare earth elements (La or Nd), there was no obvious change on reaction temperature. But for the In contained solders, the reaction temperatures was slightly decreased. By doping rare earth element (La or Nd), the ultimate tensile strength (UTS) of the solder increases to 97.8 MPa, and the elongation of the alloys is close to 30%. By doping In, the ultimate tensile strength (UTS) of the solder increases to 90 MPa, and the elongation of the alloys had no obviously change.","PeriodicalId":234537,"journal":{"name":"2005 6th International Conference on Electronic Packaging Technology","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125086962","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Through wafer via technology for 3-D packaging","authors":"Guoqiang Feng, Xiao Peng, Jian Cai, Shuidi Wang","doi":"10.1109/ICEPT.2005.1564661","DOIUrl":"https://doi.org/10.1109/ICEPT.2005.1564661","url":null,"abstract":"Through wafer via fabrication has been one of the key technologies for 3-D packaging and microsystem packaging. Four different through wafer via fabrication technologies and applications are reviewed, such as laser drilling, deep reactive ion etching (DRIE), photo assisted electro chemical etching (PAECE) and KOH etching. Especially, KOH etching is widely used in bulk micromachining of microelectromechanical system (MEMS) fabrication and featured with anisotropic etching of silicon. Through wafer via technology based on double-sided KOH etching is presented, which needs double-sided alignment exposure. A SiO/sub 2/ layer is deposited by PECVD for insulation layer and then TiW/Cu sputtering and Cu electroplating are used to deposit conductive layers. In order to reroute the metal layer of silicon wafer with vias, photosensitive dry film and liquid photoresist exposure are tested.","PeriodicalId":234537,"journal":{"name":"2005 6th International Conference on Electronic Packaging Technology","volume":"240 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121968121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Study on Optimizing Material Parameters in the Acoustic-Vibration Sensors Isolation Packaging System","authors":"Y. Jinghua, Lu Guangjun, Gong Chunqing, L. Xiaowei, L. Qingquan","doi":"10.1109/ICEPT.2005.1564742","DOIUrl":"https://doi.org/10.1109/ICEPT.2005.1564742","url":null,"abstract":"The acoustic-vibration sensors system is a kind of MEMS devices, which has a potential application prospect and its packaging plays key part in the fabrication process. The double J-Iike package model for isolating the acoustic sensor has been chosen while packaging the acoustic-vibration sensors system in this paper. By using the finite element analysis software ANSYS 5.7, modal analysis has been applied on the package model to analyze the relationship between the isolating material parameters and the natural frequencies of the model, which is the key physical quantity for isolation. The results show that the first three natural frequencies increase with the increase of the Young's modulus Y of the isolating material rubber, and they don't change evidently when the Poisson's ration mu increase and they decrease with the increase of Density phi . The optimized material parameters have been gained: Y = 1.0 times 106 N/m2, mu = 0.49 and phi = 1.2 times 103 kg/m3","PeriodicalId":234537,"journal":{"name":"2005 6th International Conference on Electronic Packaging Technology","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122313585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Interfacial Reaction between Lead-free Solder Ball and Au/Ni/Cu Pad during Laser Reflow Soldering","authors":"Yarong Chen, Yanhong Tian, Chunqing Wang","doi":"10.1109/ICEPT.2005.1564748","DOIUrl":"https://doi.org/10.1109/ICEPT.2005.1564748","url":null,"abstract":"The interfacial reaction between Sn-Ag-Cu and Sn-Ag lead-free solder balls and Au/Ni/Cu pads in laser reflow process are presented in this paper. A continuous intermetallic compound layer and some needle-like AuSn4 were observed at the interface of solder and pad, their morphology and distribution were strongly dependent on the laser input energy. Some voids were observed at the interface of solder joints when using laser as the heating source and they weakened the joints. The formation of voids maybe caused by the unique properties of laser","PeriodicalId":234537,"journal":{"name":"2005 6th International Conference on Electronic Packaging Technology","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127718407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A study on statistical process control technology applied in reflow soldering processes","authors":"Wu Zhao-hua","doi":"10.1109/ICEPT.2005.1564739","DOIUrl":"https://doi.org/10.1109/ICEPT.2005.1564739","url":null,"abstract":"SPC (statistical process control) does beforehand control for produce process through symbolic statistics. Compared with usual ex-post control, it can reduce loss and decrease failure rate effectively. In this paper, factors of SPC of reflow soldering processes were analyzed; SPC project of reflow soldering processes was confirmed; SPC models of reflow soldering processes were built; SPC of reflow soldering processes was achieved by MINITAB.","PeriodicalId":234537,"journal":{"name":"2005 6th International Conference on Electronic Packaging Technology","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121159744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Simulation Study of bump metallization on the stress and strain distributions of ACF interconnections for flip-chip-on-flex (COF) applications","authors":"S. Su, K. Zhao, S. Ma, J.H. Zhang","doi":"10.1109/ICEPT.2005.1564745","DOIUrl":"https://doi.org/10.1109/ICEPT.2005.1564745","url":null,"abstract":"Anisotropic conductive films (ACFs) are composed of an adhesive polymer matrix and fine conductive fillers using metallic particle or metal-coated polymer balls. Flip chip interconnection using ACF is being widely used in the electronic packaging. In this paper, two-dimensional nonlinear finite element analysis model was built to simulate effects of bumps' metallization on the stress and strain distributions of ACF interconnections for flip-chip-on-flex (COF) applications. The simulation results show that the bump metallization has big influence on the stress and strain. Under the thermal mechanical simulation, the stress is mainly relied on the Young's modulus of the bump while the strain is mainly depended on the CTE of the bump. In some kinds of bump/pad metallization, such as gold, nickel and copper, the copper has smaller stress, only bigger than gold, and minimum strain. If both chip bump and substrate bump fabricated by same copper, the galvanic corrosion, which occurs between two different metals and the main cause attributed to the shift of the contact resistance of ACF, does not exist. Regarding the cost and reliability synchronously, the copper may be the better substitute of gold as bump material in flip chip using ACF","PeriodicalId":234537,"journal":{"name":"2005 6th International Conference on Electronic Packaging Technology","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126199908","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Smart PCBs manufacturing technologies","authors":"T. Loner, A. Neumann, L. Bottcher, A. Pahl, A. Ostmann, R. Aschenbrenner, H. Reichl","doi":"10.1109/ICEPT.2005.1564633","DOIUrl":"https://doi.org/10.1109/ICEPT.2005.1564633","url":null,"abstract":"The inherent functionality of a printed wiring board can be dramatically increased by embedding electronic components into the board. For resistors, capacitors and inductors technological turnkey solutions are offered by major manufacturers and also technologies are under development. Application examples for passives integration into flexible PCBs are given. A further boost of functionality is accomplished by the integration of active chips into the board. An overview of different approaches and the respective sets of enabling technologies for the integration of chips into the board are given. Two of the approaches for the chip integration into the board are discussed in detail. A prerequisite for those technologies is the chip thinning, which is now available as a commercial service for chip thicknesses down to 20 /spl mu/m. In the chip in polymer (CIP) approach the thin chip is precisely positioned and soundly attached onto the board surface. After lamination of a copper coated resin foil via contacts are drilled through the laminate to the contact pads of the chip. The transfer of precise chip position parameters with respect to the board is essential for this step. The wiring on the laminate foil to the chip and to other components is subsequently structured. Process parameters and results are presented. For the embedding of chips into flexible PCBs the chip is flipped onto the substrate surface and thermode bonded. The process implies soldering. Therefore electroless Ni(P) is deposited onto the Al bond pads of the chip which is subsequently covered with small caps of solder. The solder cap heights are in the range of 4 to 8 /spl mu/m in order to keep the interconnection height low. The solder joint is realized by thermode bonding of the chip onto the structured wiring of the substrate using no-flow underfiller. The chip containing layer is then laminated and contacted to outer layers of the board by conventional through hole technique. An assessment of the advantages and disadvantages of both approaches are given on the status of our present understanding of the technological challenges.","PeriodicalId":234537,"journal":{"name":"2005 6th International Conference on Electronic Packaging Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131061607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}