2005 6th International Conference on Electronic Packaging Technology最新文献_第9页

Design and simulation of a macro-micro dual-drive high acceleration precision XY-stage for IC bonding technology

2005 6th International Conference on Electronic Packaging Technology Pub Date : 2005-08-30 DOI: 10.1109/ICEPT.2005.1564689

D. Jie, Lining Sun, Yanjie Liu, Yuhong Zhu, H. Cai

{"title":"Design and simulation of a macro-micro dual-drive high acceleration precision XY-stage for IC bonding technology","authors":"D. Jie, Lining Sun, Yanjie Liu, Yuhong Zhu, H. Cai","doi":"10.1109/ICEPT.2005.1564689","DOIUrl":"https://doi.org/10.1109/ICEPT.2005.1564689","url":null,"abstract":"A macro-micro dual-drive high acceleration precision XY-stage is presented in this paper. Combining macro with micro actuator, a system of large workspace and high acceleration with high resolution of motion is developed. Two linear voice coil motors (VCM) are used into the macro motion, and two PZT-driven micro stages of high frequency are mounted on each motor to compensate the position error. A novel elastic decoupling mechanism is used in the stage to avoid the moving gap. The high resolution linear encoder is integrated into the closed-loop feedback, which is used to measure the position of the output end of macro stage and micro stage. By using the mechanical dynamic simulation and FEA method, the decoupling mechanism and the micro mechanism are optimized, and the dynamic characteristics of the high acceleration stage are investigated, which is based on the rigid-flexible dynamic analysis of mechanical system. The simulation results show that this new configuration allows a workspace of 25/spl times/25mm/sup 2/ and an acceleration exceeding 100m/s/sup 2/ with a resolution of motion better than 10nm. The significantly improved performance of the XY-stage can meet the requirement of the rapid development of IC bonding technology.","PeriodicalId":234537,"journal":{"name":"2005 6th International Conference on Electronic Packaging Technology","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128532057","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 17

Thermo-mechanical Reliability Study of High I/Os Flip Chip On Laminated Substrate Based on FEA, RSM and Interfacial Fracture Mechanics 基于FEA、RSM和界面断裂力学的层合基板高I/ o倒装芯片热-机械可靠性研究

2005 6th International Conference on Electronic Packaging Technology Pub Date : 2005-08-30 DOI: 10.1109/ICEPT.2005.1564669

Yingjun Cheng, Gaowei Xu, Dapeng Zhu, Xiaoqin Lin, L. Luo

{"title":"Thermo-mechanical Reliability Study of High I/Os Flip Chip On Laminated Substrate Based on FEA, RSM and Interfacial Fracture Mechanics","authors":"Yingjun Cheng, Gaowei Xu, Dapeng Zhu, Xiaoqin Lin, L. Luo","doi":"10.1109/ICEPT.2005.1564669","DOIUrl":"https://doi.org/10.1109/ICEPT.2005.1564669","url":null,"abstract":"This paper described a comprehensive study of thermo-mechanical reliability of high input/outputs (I/Os) flip-chip on laminated substrate by using finite element analysis(FEA), response surface methodology(RSM) and interfacial fracture mechanics. Accelerated thermal cycling(ATC) tests for six specimens with different structures and materials were conducted firstly to determine the fatigue life and failure mechanism of the solder joints. Two-dimensional and Three-dimensional FEA corresponding to ATC tests were then conducted individually to analyze the mechanical behavior of the package under ATC conditions. Global-local FEA approach was used because of the large number of solder bumps and the complicated structure of the package. The simulation results of FEA accorded with the tests results well and a fatigue life model in related with accumulated strain energy density was built to estimate the solder joint fatigue life of the package. The combined effect of structural parameters including pad diameter, pad thickness, solder mask open, solder mask thickness and standoff height on the solder joint fatigue life were analyzed by the integration of two-dimensional FEA and central composite design (CCD) based RSM, and a response surface model was established to make the optimization. Due to imperfect manufacturing process, very small interfacial cracks commonly exist between the interface of solder joint and copper pad after reflow, the interfacial fracture behavior of the crack for different crack lengths under ATC conditions were investigated with two-dimensional FEA. Interfacial fracture mechanics and crack surface displacement extrapolation method were used to analyze the variations of strain energy release rate and phase angle at the crack tip","PeriodicalId":234537,"journal":{"name":"2005 6th International Conference on Electronic Packaging Technology","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127375301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Effects of alloying elements on the characteristics of Sn-Zn lead-free solder 合金元素对Sn-Zn无铅焊料特性的影响

2005 6th International Conference on Electronic Packaging Technology Pub Date : 2005-08-30 DOI: 10.1109/ICEPT.2005.1564675

Xi Chen, Ming Li, X. Ren, D. Mao

引用次数: 10

The Effect of Moisture on the Critical Defect Size For Delamination Failure at the Pad/Encapsulant Interface of Plastic IC Packages Undergoing Solder Reflow 水分对回流焊塑料IC封装衬垫/封装界面分层失效临界缺陷尺寸的影响

2005 6th International Conference on Electronic Packaging Technology Pub Date : 2005-08-30 DOI: 10.1109/ICEPT.2005.1564737

A. Tay, Y.Y. Ma, G. Hu

{"title":"The Effect of Moisture on the Critical Defect Size For Delamination Failure at the Pad/Encapsulant Interface of Plastic IC Packages Undergoing Solder Reflow","authors":"A. Tay, Y.Y. Ma, G. Hu","doi":"10.1109/ICEPT.2005.1564737","DOIUrl":"https://doi.org/10.1109/ICEPT.2005.1564737","url":null,"abstract":"During the solder reflow process thermal stresses are induced in a plastic-encapsulated IC package due to the mismatch of coefficient of thermal expansion (CTE) between the plastic encapsulant, the silicon chip and the leadframe-pad. Inherent voids or defects at the interface between leadframe-pad and the encapsulant become sites of stress concentration which can result in the delamination of interfaces during solder reflow. Moreover, if the package has absorbed moisture before solder reflow, it is well known that moisture does increase the likelihood of delamination and popcorn failure. In order to assess whether a defect of a particular size would lead to delamination of the pad/encapsulant interface, a necessary prerequisite for popcorn failure, it would be useful to determine what the critical defect size might be and how this is affected by moisture. This is the main objective of this paper. A 160-leaded PQFP was used as the test vehicle in this investigation. The mechanics of delamination growth along the pad/encapsulant interface was studied by varying the initial delamination from 0.1 mm to 3.5 mm. The analysis was done for packages with and without the die. It was found that G increased and reached a maximum before declining with further increase of delamination size. It is significant to note that the point when the maximum G occurred was when the tip of the delamination was just below the die edge. The effects of using different leadframe materials were studied. Alloy 42 was found to give a higher value of G than copper, leading to increased tendency to delamination. It was also found that increasing levels of moisture decreases the critical crack size for delamination","PeriodicalId":234537,"journal":{"name":"2005 6th International Conference on Electronic Packaging Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129049824","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Advances in high density interconnect substrate and printed wiring board technology 高密度互连基板和印刷线路板技术的进展

2005 6th International Conference on Electronic Packaging Technology Pub Date : 2005-08-30 DOI: 10.1109/ICEPT.2005.1564730

Fuhan Liu, V. Sundaram, B. Wiedenman, R. Tummala

引用次数: 10

Micromachined Packaging for Ultrasonic Transducers with Particle Restraint Mechanisms 具有粒子约束机制的超声换能器的微机械封装

2005 6th International Conference on Electronic Packaging Technology Pub Date : 2005-08-30 DOI: 10.1109/ICEPT.2005.1564684

Hsing-Cheng Chang, C. Lai, Hsien-Hui Tseng, Yen-Ju Chen

引用次数: 0

An application of MCM technology MCM技术的一个应用

2005 6th International Conference on Electronic Packaging Technology Pub Date : 2005-08-30 DOI: 10.1109/ICEPT.2005.1564613

Weiping Jing, Xiaochun Wu, Ling Sun

{"title":"An application of MCM technology","authors":"Weiping Jing, Xiaochun Wu, Ling Sun","doi":"10.1109/ICEPT.2005.1564613","DOIUrl":"https://doi.org/10.1109/ICEPT.2005.1564613","url":null,"abstract":"With the emphasis on compactness in consumer electronic products, it is essential for electronic engineers to implement integrated systems. In this paper, an approach based on MCM technology, which implemented six discrete chips arranged in a single-package, is presented. This approach improved the integration of electronic system and met the demand of compactness in consumer electronic products. Among these discrete chips, two high-speed operational amplifiers with two chips of digital function were mounted on silicon substrate by using the silicon-on-silicon MCM technology, and the cheaper 3 /spl mu/m metal gate CMOS technology was chosen to fabricate the silicon substrate. The Zeni EDA layout tool was used to design metal lines on the silicon substrate for interconnections between chips. Because the clock frequency of this system is above 100MHz, it is necessary to consider that the wire bonds, the package leads, the pins and the traces on silicon substrate can create signal-integrity problems, which prevent products from working correctly. The Agilent ADS momentum tool was used to simulate S-parameters of high frequency signal lines in silicon substrate, and the distance between the adjacent signals is optimized to minimize the coupling. Besides the design for interconnects, the heat transfer design of MCM package is also important. By using the Autotherm tool of Mentor Graphics' PCB Boardstation products, the thermal distribution of this system was analyzed, and the result indicated that if the other two high power chips were also arranged on the silicon substrate, the whole system was destroyed. Therefore, they were directly mounted on the copper lead frame, which is useful for heat transfer. The practical application implies that multiple bare dice implemented in different technology can be packaged into a standard IC package and works well.","PeriodicalId":234537,"journal":{"name":"2005 6th International Conference on Electronic Packaging Technology","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129463186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A microjet array cooling for the thermal management of active radar systems 用于主动雷达系统热管理的微射流阵列冷却

2005 6th International Conference on Electronic Packaging Technology Pub Date : 2005-08-30 DOI: 10.1109/ICEPT.2005.1564700

Zhigang Lin, Xiaojun Wang, Sheng Liu

{"title":"A microjet array cooling for the thermal management of active radar systems","authors":"Zhigang Lin, Xiaojun Wang, Sheng Liu","doi":"10.1109/ICEPT.2005.1564700","DOIUrl":"https://doi.org/10.1109/ICEPT.2005.1564700","url":null,"abstract":"Next-generation active radar systems are employing high power density, high temperature electronic devices such as those based on wide bandgap GaN semiconductors, requiring more advanced thermal management technology that is capable of providing higher heat dissipation and a more accurate temperature control. An innovative microjet cooling concept, bottom-side microjet array cooling (BSMAC), is proposed to cope with the demanding thermal management imposed by active radar systems. Compared with current or other emerging cooling techniques, the BSMAC has the advantages including high thermal performance, low cost and easiness to be incorporated into the currently used package structure and processing. A numerical simulation is conducted to investigate the thermal performance of the BSMAC. For the numerical study, a commercial code, FLUNET, is used to model a 3D chip array package structure with a BSMAC heatsink. The convection heat transfer is analyzed and some influential parameters are evaluated. The numerical results demonstrate the superior thermal performance of the BSMAC heatsink that is able to dissipate high heat power with a uniform temperature distribution among chips.","PeriodicalId":234537,"journal":{"name":"2005 6th International Conference on Electronic Packaging Technology","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133536266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Lifetime Assessment of Solder Joints of BGA Package in Board Level Drop Test BGA封装在板位跌落试验中焊点寿命评估

2005 6th International Conference on Electronic Packaging Technology Pub Date : 2005-08-30 DOI: 10.1109/ICEPT.2005.1564747

Lou Haohuan, Qu Xin, Chen Zhaoyi, Wang Jiaji, Taekoo Lee, Hui Wang

{"title":"Lifetime Assessment of Solder Joints of BGA Package in Board Level Drop Test","authors":"Lou Haohuan, Qu Xin, Chen Zhaoyi, Wang Jiaji, Taekoo Lee, Hui Wang","doi":"10.1109/ICEPT.2005.1564747","DOIUrl":"https://doi.org/10.1109/ICEPT.2005.1564747","url":null,"abstract":"Leaded and lead-free BGA packages were tested in board level drop test defined in the JEDEC standard. The results of experiment were employed to modify the Darveaux model to extend its application to the drop test by re-calculating the values of the parameters contained in this model. FEA models with different materials, height and pitch of solder balls were established. The characteristic of the impact applied on the PCB assembly in the drop test is the very high peak acceleration and very short pulse duration. The stress and strain of the typical nodes in these models were calculated in LS-DYNA, which is very appropriate for the simulations under these conditions. The average strain energy density was also calculated to predict the lifetime of solder joints in these different material and geometrical conditions through this modified Darveaux model. The experiment and simulation reveal that the solder joints in the corners of the package suffer much higher plastic strain and are more susceptible to fail. The mainly failure mechanism in board level drop test is the plastic-strain-induced crack at the interface between the solder balls and the pads in the packages. Lead-free solder joints have longer lifetime in board level drop test than leaded ones because of their relatively higher elastic modulus and yield stress. Optimal height and pitch of solder balls exist, which lead to lowest plastic strain and best performance in the drop test","PeriodicalId":234537,"journal":{"name":"2005 6th International Conference on Electronic Packaging Technology","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133563736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Comprehensive Warpage Analysis of Stacked Die MEMS Package in Accelerometer Application 加速度计中堆叠式MEMS封装的综合翘曲分析

2005 6th International Conference on Electronic Packaging Technology Pub Date : 2005-08-30 DOI: 10.1109/ICEPT.2005.1564716

Xueren Zhang, T. Y. Tee, J. Luan

引用次数: 9