Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium最新文献_第7页

Thick-film intelligent sensors using new Du Pont and ESL high technology materials 厚膜智能传感器采用新的杜邦和ESL高科技材料

Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium Pub Date : 1997-10-13 DOI: 10.1109/IEMT.1997.626904

J. Fitt, J. Gondek, Zygmunt Parzelka, W. Zaraska

引用次数: 1

Silicon device pad design considerations for solder flip chip applications 焊接倒装芯片应用的硅器件衬垫设计考虑

Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium Pub Date : 1997-10-13 DOI: 10.1109/IEMT.1997.626936

R. Kubin, V. Ho

引用次数: 0

Thermal enhancement and reliability of 40 mm EPBGA packages with interface materials 采用界面材料的40mm EPBGA封装的热增强和可靠性

Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium Pub Date : 1997-10-13 DOI: 10.1109/IEMT.1997.626948

Z. Celik, D. Copeland, A. Mertol

引用次数: 2

Kinetics of flux residue formation in a humid environment 湿润环境中通量残留物形成动力学

Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium Pub Date : 1997-10-13 DOI: 10.1109/IEMT.1997.626891

A. Sinni, M. A. Palmer

引用次数: 6

Integrated development and manufacturing methodology for advanced power MOSFETs 先进功率mosfet的集成开发和制造方法

Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium Pub Date : 1997-10-13 DOI: 10.1109/IEMT.1997.626867

M. Kasem

引用次数: 0

High reliability assembly of chip scale packages 芯片级封装的高可靠性组装

Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium Pub Date : 1997-10-13 DOI: 10.1109/IEMT.1997.626930

J. Partridge, C. Hart, P. Boysan, B. Surratt, R. Foehringer

{"title":"High reliability assembly of chip scale packages","authors":"J. Partridge, C. Hart, P. Boysan, B. Surratt, R. Foehringer","doi":"10.1109/IEMT.1997.626930","DOIUrl":"https://doi.org/10.1109/IEMT.1997.626930","url":null,"abstract":"Ball Grid Array (BGA) packages with 1.27 mm pitch arrays are now being extended to fine pitch BGAs, or Chip Scale Packages (CSP) with ball diameters of 0.3 mm and array pitches as small as 0.5 mm. The current work analyzes the impact of integrating such packages into a high volume SMT assembly line and examines the impact of process and board variables on the reliability of the total assembly. The CSP chosen for the current study was a 0.75 mm pitch CSP scheduled to replace the 0.5 mm lead pitch Thin Small Outline Package (TSOP) currently used in high volume, small form factor, flash memory products. The CSP dimensions of approximately 5.6 mm by 7.4 mm represents an 80% reduction in package area compared to the traditional TSOP, with a footprint of 12 mm by 20 mm. The study examines the effect of solder paste printing parameters, flux-only assembly, and printed circuit board surface finishes such as immersion gold and solder-leveling. Solder paste volume measurements were made on over 2800 individual CSP pads during the builds using an in-line, automated laser scanning profilometer. Reliability test vehicles were assembled using CSPs, TSOPs and other surface mount components, prior to performing accelerated thermal cycling tests from 0/spl deg/C to 100/spl deg/C, and 40/spl deg/C to 85/spl deg/C. CSP placements were performed using optimized high speed chip placers to place CSPs at rates of up to 5 parts per second. Interim reliability test results after four months of testing are presented with a discussion of TSOP versus MicroBGA package construction.","PeriodicalId":227971,"journal":{"name":"Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127606541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A graph-based disassembly sequence planning for EOL product recycling 基于图的EOL产品回收拆解顺序规划

Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium Pub Date : 1997-10-13 DOI: 10.1109/IEMT.1997.626890

H. Zhang, T. Kuo

{"title":"A graph-based disassembly sequence planning for EOL product recycling","authors":"H. Zhang, T. Kuo","doi":"10.1109/IEMT.1997.626890","DOIUrl":"https://doi.org/10.1109/IEMT.1997.626890","url":null,"abstract":"Disassembly sequence planning is an essential issue for end-of-life (EOL) product recycling. Wide diffusion of consumer goods and shortening of product life-cycle have caused an increasing quantity of used products being discarded. The most evident effect is that landfill capacity is being used up. This revolves that a systematic technology in recycling is imperative. This paper developed a graph based heuristic approach for the product recycling. The model is embedded on a graph representation which is obtained by generating disassembly sequences. With graph representation, the problem of identifying the disassembly sequence planning is transformed into a graph search problem. By solving the graph search problem, one can determine the termination of disassembly and generate the disassembly sequence. The disposition of end-of-life product is becoming very important issues recently. The proposed graph-based approach is to find the feasible disassembly sequences from the CAD system directly and automatically. The benefit is to provide some useful information for the designer to evaluate the disassembly problem during the design stage.","PeriodicalId":227971,"journal":{"name":"Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125630881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 58

Heat slug attach: a cyanate ester based solution 热塞剂:一种氰酸酯基溶液

Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium Pub Date : 1997-10-13 DOI: 10.1109/IEMT.1997.626945

C. Edwards, P. Nguyen, J. Kennedy

引用次数: 0

Low temperature soldering 低温焊接

Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium Pub Date : 1997-10-13 DOI: 10.1109/IEMT.1997.626966

Z. Mei, F. Hua, J. Glazer, C. Key

{"title":"Low temperature soldering","authors":"Z. Mei, F. Hua, J. Glazer, C. Key","doi":"10.1109/IEMT.1997.626966","DOIUrl":"https://doi.org/10.1109/IEMT.1997.626966","url":null,"abstract":"Low temperature soldering may reduce the cost for surface mount electronic assembly by using low cost electronic components and substrate materials. It also provides options for step soldering, and reduces the risk of thermally induced damages. A vast amount of Sn-Pb-Bi-In alloys are available for any given melting temperature (liquidus) between 50/spl deg/C and 183/spl deg/C. Currently available water clean or no-clean fluxes, however, are not suitable for low temperature soldering, because they are activated at temperature higher than 150/spl deg/C. Two solderability test methods were used to evaluate the newly developed fluxes for low temperature soldering: (a) spreading test to compare the relative strength of the fluxes, and (b) wetting balance to determine the activation temperature of the fluxes. The mechanical properties (shear strength, creep, isothermal and thermal fatigue) of several common low temperature solders were determined. Prototypes of PCBs assembled with several low temperature solders were successfully built and passed typical product qualification tests. Potential problems for low temperature soldering are the poor adhesion strength of the low temperature solders to Alloy 42 leaded components, and exceptional grain growth and early thermal failure when 58Bi-42Sn was used to solder on Sn-Pb surface.","PeriodicalId":227971,"journal":{"name":"Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133933862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 19

Macro model development as a bridge between factory level simulation and LP enterprise systems 宏观模型开发是工厂级仿真与LP企业系统之间的桥梁

Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium Pub Date : 1997-10-13 DOI: 10.1109/IEMT.1997.626953

R. Allison, J. Yu, L. Tsai, Chih-Ming Liu, M. Drummond, D. Kayton, T. Sustae, J. Witte

引用次数: 4