2020 21st International Symposium on Quality Electronic Design (ISQED)最新文献_第4页

Learning-Enabled NoC Design for Heterogeneous Manycore Systems 异构多核系统的学习型NoC设计

2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-03-01 DOI: 10.1109/ISQED48828.2020.9137000

R. Kim

引用次数: 0

Fault Attack Detection in AES by Monitoring Power Side-Channel Statistics 基于功率侧信道统计的AES故障攻击检测

2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-03-01 DOI: 10.1109/ISQED48828.2020.9136981

A. Shylendra, Priyesh Shukla, S. Bhunia, A. Trivedi

{"title":"Fault Attack Detection in AES by Monitoring Power Side-Channel Statistics","authors":"A. Shylendra, Priyesh Shukla, S. Bhunia, A. Trivedi","doi":"10.1109/ISQED48828.2020.9136981","DOIUrl":"https://doi.org/10.1109/ISQED48828.2020.9136981","url":null,"abstract":"Differential Fault Analysis (DFA) is a cryptoanalysis technique to extract internal state of crypto-algorithms by inducing and propagating the faults during encryption. In this work, we present a low-power CMOS based mixed-signal framework for on-line DFA-based clock-glitch attack detection by monitoring power side-channel statistics. We discuss non-parametric kernel density estimation (KDE)-based technique to develop statistical model of power side-channel leakage. Clock-glitch attack is detected by identifying the low-likelihood samples using the developed statistical model. We have implemented KDE using CMOS current-mode Gilbert Gaussian Circuit-based Gaussian kernels. AES-128 was implemented on ARM Microcontroller by ST Microelectronics and Chip Whisperer-lite board was used to launch clock-glitch attack as well as capture power side-channel traces. We have evaluated the performance of our approach using power side-channel trace with clock-glitch attacks. We have adopted sliding window approach to update the statistical model in real-time. Discussed CMOS-based mixed-signal framework was designed at 45nm technology node and proposed design on an average consumes $simmathbf{210}mumathbf{W}$ at 2 MHz sampling frequency while utilizing 10 recently validated samples for PDF estimation. Moreover, discussed approach allows programming of parameters such as kernel standard deviation $(Kernel_{SD})$ and likelihood-threshold $(LH_{Thres})$ for high efficiency detection.","PeriodicalId":225828,"journal":{"name":"2020 21st International Symposium on Quality Electronic Design (ISQED)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123101165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Hierarchical Improvement of Quantum Approximate Optimization Algorithm for Object Detection: (Invited Paper) 目标检测中量子近似优化算法的层次改进(特邀论文)

2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-03-01 DOI: 10.1109/ISQED48828.2020.9136973

Junde Li, M. Alam, Abdullah Ash-Saki, Swaroop Ghosh

{"title":"Hierarchical Improvement of Quantum Approximate Optimization Algorithm for Object Detection: (Invited Paper)","authors":"Junde Li, M. Alam, Abdullah Ash-Saki, Swaroop Ghosh","doi":"10.1109/ISQED48828.2020.9136973","DOIUrl":"https://doi.org/10.1109/ISQED48828.2020.9136973","url":null,"abstract":"Quantum Approximate Optimization Algorithm (QAOA) provides approximate solution to combinatorial optimization problems. It encodes the cost function using a $p$ -level quantum circuit where each level consists a problem Hamiltonian followed by a mixing Hamiltonian. Despite the promises, few real-world applications (besides the pedagogical MaxCut problem) have exploited QAOA. The success of QAOA relies on the classical optimizer, variational parameter setting, and quantum circuit design and compilation. In this study, we implement QAOA and analyze its performance for a broader Quadratic Unconstrained Binary Optimization (QUBO) formulation to solve real-word applications such as, partially occluded object detection problem. Furthermore, we analyze the effects of above influential factors on QAOA performance. We propose a 3-level improvement of hybrid quantum-classical optimization for object detection. We achieve more than 13X execution speedup by choosing L-BFGS-B as classical optimizer at the first level and 5.50X additional speedup by exploiting parameter symmetry and more than 1.23X acceleration using parameter regression at the second level. We empirically show that the circuit will achieve better fidelity by optimally rescheduling gate operations (especially for deeper circuits) at the third level.","PeriodicalId":225828,"journal":{"name":"2020 21st International Symposium on Quality Electronic Design (ISQED)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129519288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Electrostatic Discharge Physical Verification of 2.5D/3D Integrated Circuits 2.5D/3D集成电路静电放电物理验证

2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-03-01 DOI: 10.1109/ISQED48828.2020.9137046

D. Medhat, M. Dessouky, Diaaeldin Khalil

引用次数: 2

Reducing Impact of CNFET Process Imperfections on Shape of Activation Function by Using Connection Pruning and Approximate Neuron Circuit 利用连接剪枝和近似神经元电路降低CNFET过程缺陷对激活函数形状的影响

2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-03-01 DOI: 10.1109/ISQED48828.2020.9137023

K. Sheikh, Lan Wei

{"title":"Reducing Impact of CNFET Process Imperfections on Shape of Activation Function by Using Connection Pruning and Approximate Neuron Circuit","authors":"K. Sheikh, Lan Wei","doi":"10.1109/ISQED48828.2020.9137023","DOIUrl":"https://doi.org/10.1109/ISQED48828.2020.9137023","url":null,"abstract":"Deep Neural Networks (DNNs) based on Carbon nanotube field effect transistor (CNFET) technology can leverage the potential energy benefits of CNFET based technology in comparison to conventional Si technology. However, like other emerging materials based technologies, the current fabrication processes for CNFETs lack the quality, resulting in CNFETs suffering from process imperfections, consequently degradation in circuit-level performance. Such imperfections will cause timing failure and distort the shape of non-linear activation functions, which are vital in DNN, leading to significant degradation in classification accuracy. We utilize pruning of synaptic weights which combined with proposed approximate neuron circuit significantly reduces the chance of timing failure, and achieve better frequency of operation (speed), even using highly imperfect process. In our example, the proposed configuration with approximate neuron and pruning at a high imperfect process $(PCNT_{open}= 40%)$, in comparison to base configuration of precise neuron and no pruning with ideal process $(PCNT_{open}= 0%)$, achieves peak accuracy only 0.19% less, but significant energy-delay-product (EDP) advantage (56.7% less), at no area penalty.","PeriodicalId":225828,"journal":{"name":"2020 21st International Symposium on Quality Electronic Design (ISQED)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129437701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

CSCMAC - Cyclic Sparsely Connected Neural Network Manycore Accelerator CSCMAC -循环稀疏连接神经网络多核加速器

2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-03-01 DOI: 10.1109/ISQED48828.2020.9137013

Hirenkumar Paneliya, M. Hosseini, Avesta Sasan, H. Homayoun, T. Mohsenin

{"title":"CSCMAC - Cyclic Sparsely Connected Neural Network Manycore Accelerator","authors":"Hirenkumar Paneliya, M. Hosseini, Avesta Sasan, H. Homayoun, T. Mohsenin","doi":"10.1109/ISQED48828.2020.9137013","DOIUrl":"https://doi.org/10.1109/ISQED48828.2020.9137013","url":null,"abstract":"This paper presents an energy-efficient, domain-specific manycore accelerator also referred to as the “CSCMAC” - Cyclic Sparsely Connected Neural Network Manycore Accelerator, which effectively maps and executes deep neural networks (DNNs) compressed with cyclic sparsely connected (CSC) architectures. CSC layers are architectures that structurally compress and sparsify DNNs, which can reduce the memory footprint of fully connected (FC) layers from $O(N^{2})$ to $O(Nlog N)$ with respect to layers nodes, and is shown to be hardware implementable-friendly. We implement CSC layers for inference on a manycore unit, take advantage of their cyclic architecture, and show that their implementation in software even for a parallel-computing processor is affable. To further take advantage of their implementation simplicity, we propose customized instructions for the manycore that fuse frequently used sequences of machine codes and evaluate the optimization gained by the customization. Our experimental results using a LeNet300100 on MNIST and a Multi-Layer Perceptron (MLP) on Physical Activity Monitoring indicate that by replacing FC layers with CSC layers, we can achieve $46times$ and $6times$ compression respectively within a margin of 2% accuracy loss. A 64-cluster architecture of the CSCMAC is fully placed and routed using $65mathrm{nm}$, TSMC CMOS technology. The layout of each cluster occupies an area of $0.73 mm^{2}$ and consumes $230.2 mathrm{mW}$ power at 980 MHz clock frequency. Our proposed CSCMAC achieves $1.48times$ higher throughput and $1.49times$ lower energy compared to its equivalent predecessor manycore (PENC). Also, the CSCMAC achieves $85times$ higher throughput and consumes $66.4times$ lower energy compared to CPU implementation of the NVIDIA Jetson TX2 platform.","PeriodicalId":225828,"journal":{"name":"2020 21st International Symposium on Quality Electronic Design (ISQED)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133051736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Mining Message Flows using Recurrent Neural Networks for System-on-Chip Designs 在片上系统设计中使用递归神经网络挖掘消息流

2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-03-01 DOI: 10.1109/ISQED48828.2020.9137001

Yuting Cao, P. Mukherjee, M. Ketkar, Jin Yang, Hao Zheng

{"title":"Mining Message Flows using Recurrent Neural Networks for System-on-Chip Designs","authors":"Yuting Cao, P. Mukherjee, M. Ketkar, Jin Yang, Hao Zheng","doi":"10.1109/ISQED48828.2020.9137001","DOIUrl":"https://doi.org/10.1109/ISQED48828.2020.9137001","url":null,"abstract":"Comprehensive specifications are essential for various activities across the entire validation continuum for system-on-chip (SoC) designs. However, specifications are often ambiguous, incomplete, or even contain inconsistencies or errors. This paper addresses this problem by developing a specification mining approach that automatically extracts sequential patterns from SoC transaction-level traces such that the mined patterns collectively characterize system-level specifications for SoC designs. This approach exploits long short-term memory (LSTM) networks trained with the collected SoC execution traces to capture sequential dependencies among various communication events. Then, a novel algorithm is developed to efficiently extract sequential patterns on system-level communications from the trained LSTM models. Several trace processing techniques are also proposed to enhance the mining performance. We evaluate the proposed approach on simulation traces of a non-trivial multi-core SoC prototype. Initial results show that the proposed approach is capable of extracting various patterns on system-level specifications from the highly concurrent SoC execution traces.","PeriodicalId":225828,"journal":{"name":"2020 21st International Symposium on Quality Electronic Design (ISQED)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122266343","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Welcome to ISQED'20 欢迎来到ISQED'20

2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-03-01 DOI: 10.1109/isqed48828.2020.9136976

引用次数: 0

BNN Pruning: Pruning Binary Neural Network Guided by Weight Flipping Frequency BNN剪枝:基于权值翻转频率的剪枝二值神经网络

2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-03-01 DOI: 10.1109/ISQED48828.2020.9136977

Yixing Li, Fengbo Ren

{"title":"BNN Pruning: Pruning Binary Neural Network Guided by Weight Flipping Frequency","authors":"Yixing Li, Fengbo Ren","doi":"10.1109/ISQED48828.2020.9136977","DOIUrl":"https://doi.org/10.1109/ISQED48828.2020.9136977","url":null,"abstract":"A binary neural network (BNN) is a compact form of neural network. Both the weights and activations in BNNs can be binary values, which leads to a significant reduction in both parameter size and computational complexity compared to their full-precision counterparts. Such reductions can directly translate into reduced memory footprint and computation cost in hardware, making BNNs highly suitable for a wide range of hardware accelerators. However, it is unclear whether and how a BNN can be further pruned for ultimate compactness. As both 0s and 1s are non-trivial in BNNs, it is not proper to adopt any existing pruning method of full-precision networks that interprets 0s as trivial. In this paper, we present a pruning method tailored to BNNs and illustrate that BNNs can be further pruned by using weight flipping frequency as an indicator of sensitivity to accuracy. The experiments performed on the binary versions of a 9-layer Network-in-Network (NIN) and the AlexNet with the CIFAR-10 dataset show that the proposed BNN-pruning method can achieve 20-40% reduction in binary operations with 0.5-1.0% accuracy drop, which leads to a 15-40% runtime speedup on a TitanX GPU.","PeriodicalId":225828,"journal":{"name":"2020 21st International Symposium on Quality Electronic Design (ISQED)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116868260","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

A Survey of DMFBs Security: State-of-the-Art Attack and Defense dmfb安全调查:最先进的攻击与防御

2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-03-01 DOI: 10.1109/ISQED48828.2020.9137016

Chen Dong, Lingqing Liu, Huangda Liu, Wenzhong Guo, Xing Huang, Sihuang Lian, Ximeng Liu, Tsung-Yi Ho

引用次数: 10