Electrostatic Discharge Physical Verification of 2.5D/3D Integrated Circuits

Abstract

Technology evolution from conventional 2D to 3D integrated circuits (ICs) has faced many challenges, among them electrostatic discharge (ESD) protection device design and verification. Several studies have addressed ESD device design for 3D ICs. However, once such designs are implemented, there is a lack of automated ESD physical verification methodologies. In this paper, we propose an automated ESD layout verification solution that addresses complete 2.5D/3D IC designs. The proposed flow covers protection schemes for both external and internal input/output interfaces. Moreover, it addresses total point-to-point parasitic resistance and current density analysis for relevant ESD interconnect routes across all dies and interposer to ensure they can handle any ESD event. An ESD verification testcase demonstrates the inputs setup for the flow, and shares results for different ESD violations to prove the effectiveness of the proposed solution for both detection as well as debugging.