2020 21st International Symposium on Quality Electronic Design (ISQED)最新文献

A Morphable Physically Unclonable Function and True Random Number Generator using a Commercial Magnetic Memory 利用商用磁存储器的可变形物理不可克隆函数和真随机数发生器

2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-03-01 DOI: 10.1109/ISQED48828.2020.9136975

Mohammad Nasim Imtiaz Khan, Chak Yuen Cheng, Sung-Hao Lin, Abdullah Ash-Saki, Swaroop Ghosh

引用次数: 4

Comparative Framework for the Analysis of Thermal and Resource Management Algorithms for Multi-Core Architectures 多核架构热管理与资源管理算法分析的比较框架

2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-03-01 DOI: 10.1109/ISQED48828.2020.9137038

Moeez Akmal, Muhammad Sarmad Saeed, Muhammad Usama Sardar, Hareem Shafi, O. Hasan, Heba Khdr, J. Henkel

引用次数: 0

DOVA: A Dynamic Overwriting Voltage Adjustment for STT-RAM L1 Cache STT-RAM L1高速缓存的动态覆盖电压调整

2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-03-01 DOI: 10.1109/ISQED48828.2020.9137020

Jinbo Chen, Keren Liu, Xiaochen Guo, P. Girard, Yuanqing Cheng

{"title":"DOVA: A Dynamic Overwriting Voltage Adjustment for STT-RAM L1 Cache","authors":"Jinbo Chen, Keren Liu, Xiaochen Guo, P. Girard, Yuanqing Cheng","doi":"10.1109/ISQED48828.2020.9137020","DOIUrl":"https://doi.org/10.1109/ISQED48828.2020.9137020","url":null,"abstract":"As device integration density increases exponentially predicted by Moore's law, power consumption becomes a bottleneck for system scaling. On the other hand, leakage power of on-chip cache occupies a large fraction of the total power budget. STT-RAM is a promising candidate to replace SRAM as on-chip cache due to its ultra-low leakage power, high integration density and non-volatility. However, building L1 cache with STT-RAM still faces severe challenges especially because of its high write latency and energy overheads. Moreover, intensive accesses in L1 cache accelerate oxide breakdown and threaten the lifetime of STT-RAM significantly. In this paper, we propose a Dynamic Overwriting Voltage Adjustment (DOVA) technique for STT-RAM L1 cache. A high write voltage is used for performance critical cache lines while a low write voltage is used for other cache lines to approach an optimal trade-off between reliability and performance. Experimental results show that the proposed technique can improve cache performance up to 18%, and 9% on average with almost the same reliability level as in the case when only the low write voltage is used.","PeriodicalId":225828,"journal":{"name":"2020 21st International Symposium on Quality Electronic Design (ISQED)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124596130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Variation-Aware Heterogeneous Voltage Regulation for Multi-Core Systems-on-a-Chip with On-Chip Machine Learning 基于片上机器学习的多核片上系统的变化感知异质电压调节

2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-03-01 DOI: 10.1109/ISQED48828.2020.9136985

Joseph Riad, Jianhao Chen, E. Sánchez-Sinencio, Peng Li

引用次数: 1

How to Retrieve PUF Response from a Fabricated Chip Securely? 如何安全地从预制芯片中检索PUF响应?

2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-03-01 DOI: 10.1109/ISQED48828.2020.9137044

Aijiao Cui, Yuxi Wang

引用次数: 0

CDS-RSRAM: a Reconfigurable SRAM Architecture to Reduce Read Power with Column Data Segmentation CDS-RSRAM:一个可重构的SRAM架构，以降低读取功率与列数据分割

2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-03-01 DOI: 10.1109/ISQED48828.2020.9136993

Han Xu, Ziru Li, F. Qiao, Qi Wei, Xinjun Liu, Huazhong Yang

{"title":"CDS-RSRAM: a Reconfigurable SRAM Architecture to Reduce Read Power with Column Data Segmentation","authors":"Han Xu, Ziru Li, F. Qiao, Qi Wei, Xinjun Liu, Huazhong Yang","doi":"10.1109/ISQED48828.2020.9136993","DOIUrl":"https://doi.org/10.1109/ISQED48828.2020.9136993","url":null,"abstract":"SRAM access takes a significant part of on-chip power consumption in many signal processing systems. Reconfigurable data-adaptive SRAMs (RSRAM) can save considerable read power by utilizing data patterns. In these RSRAM designs, the column size (i.e., the number of cells in one column) of the cell array defines the granularity of data pattern exploitation. However, the column size cannot be too small due to circuit constraints, which makes finer-grained data features hidden and suppresses RSRAM's advantage of low-power read. In this paper, we propose a reconfigurable SRAM architecture with column data segmentation (CDS-RSRAM) to break this limitation to exploit better data patterns without decreasing the column size. We partition data in one column into several segments and perform statistical analysis on every segment respectively. Each data segment has one exclusive flag bit to control its working mode while reading. This architecture can leverage data patterns at finer granularity and magnify RSRAM's advantage of low-power read. We also make a thorough overhead analysis and improve the mode decision strategy to minimize the power overheads. The simulation results show that compared with the original RSRAM, the proposed architecture saves up to 36.8% read power with 8.8% area overhead. Compared with 8T SRAM, the total power saving can be up to 77.1%.","PeriodicalId":225828,"journal":{"name":"2020 21st International Symposium on Quality Electronic Design (ISQED)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125702499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Stress-Induced Performance Shifts in Flexible System-in-Foils Using Ultra-Thin Chips 使用超薄芯片的柔性系统箔的应力诱导性能变化

2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-03-01 DOI: 10.1109/ISQED48828.2020.9136992

Tengtao Li, S. Sapatnekar

引用次数: 1

EGAN: A Framework for Exploring the Accuracy vs. Energy Efficiency Trade-off in Hardware Implementation of Error Resilient Applications EGAN:一个探索在硬件实现中误差弹性应用的精度与能源效率权衡的框架

2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-03-01 DOI: 10.1109/ISQED48828.2020.9137041

Marzieh Vaeztourshizi, M. Kamal, M. Pedram

{"title":"EGAN: A Framework for Exploring the Accuracy vs. Energy Efficiency Trade-off in Hardware Implementation of Error Resilient Applications","authors":"Marzieh Vaeztourshizi, M. Kamal, M. Pedram","doi":"10.1109/ISQED48828.2020.9137041","DOIUrl":"https://doi.org/10.1109/ISQED48828.2020.9137041","url":null,"abstract":"In this paper, we propose a framework, which is called EGAN, for exploring the trade-off between accuracy and energy efficiency in hardware implementation of error resilient applications. EGAN automatically extracts the Pareto frontier (PF) of approximate implementations of an error resilient application based on the data flow graph (DFG) of the application as well as the accuracy and energy consumption of the available approximate/exact components. The framework explores different implementation configurations heuristically to find the best energy efficient implementation of the input application under various output accuracies. The proposed framework, which works by generating some random configurations, clustering them and suggesting some neighboring configurations, reduces the search space considerably. As a result, EGAN achieves a significant reduction in the number of explored configurations compared to the exhaustive (exact) approach while achieving near-optimal results. The efficacy of the proposed framework is assessed using three DSP applications consisting of Sobel edge detector, Finite Inverse Response (FIR) filter and Discrete Cosine Transform (DCT). The studies show that in the worst-case (DCT application with 42 components) EGAN takes 89 hours to extract the PF whereas the exact approach takes 5 million years.","PeriodicalId":225828,"journal":{"name":"2020 21st International Symposium on Quality Electronic Design (ISQED)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114704012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Performance Boost Scheme with Activated Dummy Fin in 12-nm FinFET Technology for High-Performance Logic Application 用于高性能逻辑应用的12nm FinFET技术中具有激活假鳍的性能提升方案

2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-03-01 DOI: 10.1109/ISQED48828.2020.9136997

M. Ichihashi, J. Zeng, Y. Woo, Xuelian Zhu, Chenchen Wang, James Mazza

引用次数: 0

IMU-based Smart Knee Pad for Walking Distance and Stride Count Measurement 基于imu的智能护膝，用于步行距离和步数测量

2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-03-01 DOI: 10.1109/ISQED48828.2020.9136969

Teng-Chia Wang, Yan-Ping Chang, Chun-Jui Chen, Yun-Ju Lee, Chia-Chun Lin, Yung-Chih Chen, Chun-Yao Wang

引用次数: 1