M. Ichihashi, J. Zeng, Y. Woo, Xuelian Zhu, Chenchen Wang, James Mazza
{"title":"Performance Boost Scheme with Activated Dummy Fin in 12-nm FinFET Technology for High-Performance Logic Application","authors":"M. Ichihashi, J. Zeng, Y. Woo, Xuelian Zhu, Chenchen Wang, James Mazza","doi":"10.1109/ISQED48828.2020.9136997","DOIUrl":null,"url":null,"abstract":"This paper demonstrates performance enhancement with activated dummy fins based on a 12-nm FinFET technology definition for high-performance logic module design. The proposed scheme uses a double-height cell structure with two additional active fins enabled compared to traditional single-height cell stacking. The increase in total active fins in the proposed scheme results in higher effective transistor density and better cell performance. Through Design and Technology Co-Optimization, the parasitic capacitance of these proposed cells can be further decreased, with a NAND $2\\times 4$ cell yielding about 20% lower parasitic capacitance per fin compared to a traditional single-height cell. The proposed scheme shows the highest efficacy for gate-dominant and complex module designs like CPUs.","PeriodicalId":225828,"journal":{"name":"2020 21st International Symposium on Quality Electronic Design (ISQED)","volume":"53 1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 21st International Symposium on Quality Electronic Design (ISQED)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISQED48828.2020.9136997","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This paper demonstrates performance enhancement with activated dummy fins based on a 12-nm FinFET technology definition for high-performance logic module design. The proposed scheme uses a double-height cell structure with two additional active fins enabled compared to traditional single-height cell stacking. The increase in total active fins in the proposed scheme results in higher effective transistor density and better cell performance. Through Design and Technology Co-Optimization, the parasitic capacitance of these proposed cells can be further decreased, with a NAND $2\times 4$ cell yielding about 20% lower parasitic capacitance per fin compared to a traditional single-height cell. The proposed scheme shows the highest efficacy for gate-dominant and complex module designs like CPUs.