2020 21st International Symposium on Quality Electronic Design (ISQED)最新文献_第2页

Synthesis and Generalization of Parallel Algorithms Considering Communication Constraints 考虑通信约束的并行算法的综合与推广

2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-03-01 DOI: 10.1109/ISQED48828.2020.9137022

Akihiro Goda, Yukio Miyasaka, A. M. Gharehbaghi, M. Fujita

引用次数: 2

Secure, Scalable and Low-Power Junction Temperature Sensing for Multi-Processor Systems-on-Chip 用于多处理器片上系统的安全、可扩展和低功耗结温传感

2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-03-01 DOI: 10.1109/ISQED48828.2020.9136996

G. A. Kumar

引用次数: 1

RARA: Dataflow Based Error Compensation Methods with Runtime Accuracy-Reconfigurable Adder 基于数据流的运行时精度可重构加法器误差补偿方法

2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-03-01 DOI: 10.1109/ISQED48828.2020.9136984

Shujuan Yin, Zheyu Liu, Guihong Li, F. Qiao, Qi Wei, Yuanfeng Wu, Lianru Gao, Xinjun Liu, Huazhong Yang

引用次数: 2

Entropy-Shield:Side-Channel Entropy Maximization for Timing-based Side-Channel Attacks 熵盾:基于时间的边信道攻击的边信道熵最大化

2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-03-01 DOI: 10.1109/ISQED48828.2020.9137008

Abhijitt Dhavlle, Raj Mehta, S. Rafatirad, H. Homayoun, Sai Manoj Pudukotai Dinakarrao

{"title":"Entropy-Shield:Side-Channel Entropy Maximization for Timing-based Side-Channel Attacks","authors":"Abhijitt Dhavlle, Raj Mehta, S. Rafatirad, H. Homayoun, Sai Manoj Pudukotai Dinakarrao","doi":"10.1109/ISQED48828.2020.9137008","DOIUrl":"https://doi.org/10.1109/ISQED48828.2020.9137008","url":null,"abstract":"The hardware systems have experienced a plethora of side-channel attacks (SCAs) in recent years with cache-based SCAs being one of the dominant threats. The SCAs exploit the architectural caveats, which invariably leak essential information during an application's execution. Shutting down the side-channels is not a feasible approach due to various restrictions, such as architectural changes and complexity. To overcome such concerns and protect the data integrity, we introduce Entropy-Shield in this work. The proposed Entropy-Shield aims to maximize the entropy in the leaked side-channel information rather than attempting to close the side-channels. To achieve this, the proposed Entropy-Shield introduces carefully and sensibly crafted perturbations into the victim application, thereby increasing the entropy of the information obtained by the attacker to deduce the secret key, while the information being observed looks legit yet futile. This methodology has been successfully tested on cache targeted SCAs such as Flush+Reload and Flush+Flush and the key information retrieved by the attacker is shown to be ultimately futile, indicating the success of proposed Entropy-Shield.","PeriodicalId":225828,"journal":{"name":"2020 21st International Symposium on Quality Electronic Design (ISQED)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127638028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Saving Time and Energy Using Partial Flash Memory Operations in Low-Power Microcontrollers 在低功耗微控制器中使用部分闪存操作节省时间和能源

2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-03-01 DOI: 10.1109/ISQED48828.2020.9137034

Prawar Poudel, A. Milenković

引用次数: 1

Signal Selection Heuristics for Post-Silicon Validation 后硅验证的信号选择启发式方法

2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-03-01 DOI: 10.1109/ISQED48828.2020.9137037

Suprajaa Tummala, Xiaobang Liu, R. Vemuri

引用次数: 2

Spintronics-based Reconfigurable Ising Model Architecture 基于自旋电子学的可重构Ising模型架构

2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-03-01 DOI: 10.1109/ISQED48828.2020.9137043

Ankit Mondal, Ankur Srivastava

{"title":"Spintronics-based Reconfigurable Ising Model Architecture","authors":"Ankit Mondal, Ankur Srivastava","doi":"10.1109/ISQED48828.2020.9137043","DOIUrl":"https://doi.org/10.1109/ISQED48828.2020.9137043","url":null,"abstract":"The Ising model has been explored as a framework for modeling NP-hard problems, with several diverse systems proposed to solve it. The Magnetic Tunnel Junction (MTJ)-based Magnetic RAM is capable of replacing CMOS in memory chips. In this paper, we propose the use of MTJs for representing the units of an Ising model and leveraging its intrinsic physics for finding the ground state of the system through annealing. We design the structure of a basic MTJ-based Ising cell capable of performing the functions essential to an Ising solver. A technique to use the basic Ising cell for scaling to large problems is described. We then go on to propose Ising-FPGA, a parallel and reconfigurable architecture that can be used to map a large class of NP-hard problems, and show how a standard Place and Route tool can be utilized to program the Ising-Fpga. The effects of this hardware platform on our proposed design are characterized and methods to overcome these effects are prescribed. We discuss how two representative NP-hard problems can be mapped to the Ising model. Simulation results show the effectiveness of MTJs as Ising units by producing solutions close/comparable to the optimum, and demonstrate that our design methodology holds the capability to account for the effects of the hardware.","PeriodicalId":225828,"journal":{"name":"2020 21st International Symposium on Quality Electronic Design (ISQED)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134336095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

IC Design & Test 集成电路设计与测试

2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-03-01 DOI: 10.1109/isqed48828.2020.9137049

引用次数: 0

ISQED'20 Best Papers ISQED'20最佳论文

2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-03-01 DOI: 10.1109/ISQED48828.2020.9137010

Xianwei Cheng, Hui-Qun Zhao, M. Kandemir, S. Mohanty, Beilei Jiang, Marzieh Vaeztourshizi, M. Kamal, M. Pedram, Mohammad Nasim Imtiaz Khan, Chak Yuen Cheng, Sung-Hao Lin, Abdullah Ash, Swaroop Ghosh

引用次数: 0

Analytical Estimation and Localization of Hardware Trojan Vulnerability in RTL Designs RTL设计中硬件木马漏洞的分析、估计与定位

2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-03-01 DOI: 10.1109/ISQED48828.2020.9137024

S. A. Islam, Love Kumar Sah, S. Katkoori

{"title":"Analytical Estimation and Localization of Hardware Trojan Vulnerability in RTL Designs","authors":"S. A. Islam, Love Kumar Sah, S. Katkoori","doi":"10.1109/ISQED48828.2020.9137024","DOIUrl":"https://doi.org/10.1109/ISQED48828.2020.9137024","url":null,"abstract":"Offshoring the proprietary Intellectual property (IP) has recently increased the threat of malicious logic insertion in the form of Hardware Trojan (HT). A potential and stealthy HT is triggered with nets that switch rarely during regular circuit operation. Detection of HT in the host design requires exhaustive simulation to activate the HT during pre- and post-silicon. Although the nets with variable switching probability less than a threshold are primarily chosen as a good candidate for Trojan triggering, there is no systematic fine-grained approach for earlier detection of rare nets from word-level measures of input signals. In this paper, we propose a high-level technique to estimate the nets with the rare activity of arithmetic modules from word-level information. Specifically, for a given module, we use the knowledge of internal construction of the architecture to detect “low activity” and “local regions” without resorting to expensive RTL and other low-level simulations. The presented heuristic method abstracts away from the low-level details of design and describes the rare activity of bits (modules) in a word (architecture) as a function of signal statistics. The resulting quick estimates of nets in rare regions allows a designer to develop a compact test generation algorithm without the knowledge of the bit-level activity. We determine the effect of different positions of the breakpoint in the input signal to calculate the accuracy of the approach. We conduct a set of experiments on six adder architectures and four multiplier architectures. The average error to calculate the rare nets between RTL simulation and estimated values are below 2% in all architectures.","PeriodicalId":225828,"journal":{"name":"2020 21st International Symposium on Quality Electronic Design (ISQED)","volume":"4 12","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131671860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2