2020 21st International Symposium on Quality Electronic Design (ISQED)最新文献_第3页

Efficient Transfer Learning on Modeling Physical Unclonable Functions 物理不可克隆函数建模的高效迁移学习

2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-03-01 DOI: 10.1109/ISQED48828.2020.9137057

Qian Wang, Omid Aramoon, Pengfei Qiu, G. Qu

引用次数: 0

SeqL: Secure Scan-Locking for IP Protection SeqL: IP保护的安全扫描锁定

2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-03-01 DOI: 10.1109/ISQED48828.2020.9136991

S. Potluri, Aydin Aysu, Akash Kumar

引用次数: 14

Strong Anti-SAT: Secure and Effective Logic Locking 强抗sat:安全有效的逻辑锁定

2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-03-01 DOI: 10.1109/ISQED48828.2020.9136983

Yuntao Liu, Michael Zuzak, Yang Xie, Abhishek Chakraborty, Ankur Srivastava

{"title":"Strong Anti-SAT: Secure and Effective Logic Locking","authors":"Yuntao Liu, Michael Zuzak, Yang Xie, Abhishek Chakraborty, Ankur Srivastava","doi":"10.1109/ISQED48828.2020.9136983","DOIUrl":"https://doi.org/10.1109/ISQED48828.2020.9136983","url":null,"abstract":"Logic locking has been proposed as strong protection of intellectual property (IP) against security threats in the IC supply chain especially when the fabrication facility is untrusted. Such techniques use additional locking circuitry to inject incorrect behavior into the digital functionality when the key is incorrect. A family of attacks known as “SAT attacks” provides a strong mathematical formulation to find the correct key of locked circuits. Many conventional SAT-resilient logic locking schemes fail to inject sufficient error into the circuit when the key is incorrect: there are usually very few (or only one) input minterms that cause any error at the circuit output [18], [20]–[22]. The state-of-the-art stripped functionality logic locking (SFLL) [24] technique provides a wide spectrum of configurations which introduced a trade-off between security (i.e. SAT attack complexity) and effectiveness (i.e. the amount of error injected by a wrong key). In this work, we prove that such a trade-off is universal among all logic locking techniques. In order to attain high effectiveness of locking without compromising security, we propose a novel secure and effective logic locking scheme, called Strong Anti-SAT (SAS). SAS has the following significant improvements over existing techniques. (1) We prove that SAS's security against SAT attack is not compromised by increases in effectiveness. (2) In contrast to prior work which focused solely on the circuit-level locking impact, we integrate SAS-locked modules into an 80386 processor and show that SAS has a high application-level impact. (3) SAS's hardware overhead is smaller than that of existing techniques.","PeriodicalId":225828,"journal":{"name":"2020 21st International Symposium on Quality Electronic Design (ISQED)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132892228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 24

Layout Capacitance Extraction Using Automatic Pre-Characterization and Machine Learning 基于自动预表征和机器学习的布局电容提取

2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-03-01 DOI: 10.1109/ISQED48828.2020.9136970

Zhixing Li, Weiping Shi

{"title":"Layout Capacitance Extraction Using Automatic Pre-Characterization and Machine Learning","authors":"Zhixing Li, Weiping Shi","doi":"10.1109/ISQED48828.2020.9136970","DOIUrl":"https://doi.org/10.1109/ISQED48828.2020.9136970","url":null,"abstract":"The most widely adopted approach for layout capacitance extraction is pattern matching, where a layout is partitioned into small sections and matched against a pre-characterized pattern library. The capacitance formula associated with the matched pattern is used to compute the capacitance. The pattern matching approach can meet the speed and capacity requirements for large ASICs, but the pattern library and associated formula must be manually created by experienced engineers through a tedious process. For each new process node or any change to the technology profile, this process has to be repeated, causing a heavy burden on the EDA vendors and delays in PDK releases by the foundries. In this paper, we propose an automatic approach that significantly reduces the effort and time compared with the manual approach for the pattern matching method for capacitance extraction. Our approach consists of the following steps: 1) generate sample geometries that cover the problem space, 2) for each sample geometry, call a field solver to compute the capacitance value, 3) use unsupervised learning with the field solver values and foundry values as guidance to cluster geometries into patterns and derive the capacitance formula, and 4) use supervised learning to train a neural network that will be used to classify any layout geometry into a pattern in the library, which will be used at the extraction time. Experiment results show the proposed approach achieves satisfactory accuracy well above the foundry requirements and runs as fast as traditional pattern matching software. Although our approach is only demonstrated for 2D, it is the first framework using the automatic procedure and machine learning in capacitance extraction. As the interconnect structures and foundry requirements become more complex, our approach may be attractive to EDA vendors and foundries.","PeriodicalId":225828,"journal":{"name":"2020 21st International Symposium on Quality Electronic Design (ISQED)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114168039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

[ISQED Keynotes - 6 abstracts] [资讯及经济发展局主题演讲- 6项摘要]

2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-03-01 DOI: 10.1109/isqed48828.2020.9137021

引用次数: 0

Rehabilitation System for Limbs using IMUs 使用imu的肢体康复系统

2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-03-01 DOI: 10.1109/ISQED48828.2020.9137026

Chun-Jui Chen, Yi-Ting Lin, Chia-Chun Lin, Yung-Chih Chen, Yun-Ju Lee, Chun-Yao Wang

引用次数: 6

Piezoelectric CMOS Charger: Highest Output-Power Design 压电CMOS充电器:最高输出功率设计

2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-03-01 DOI: 10.1109/ISQED48828.2020.9137018

Siyu Yang, G. Rincón-Mora

引用次数: 1

A Scalable FPGA Engine for Parallel Acceleration of Singular Value Decomposition 一种并行加速奇异值分解的可扩展FPGA引擎

2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-03-01 DOI: 10.1109/ISQED48828.2020.9137055

Yu Wang, Jeong-Jun Lee, Yu Ding, Peng Li

引用次数: 6

Two-Graph Approach to Temperature Dependent Skew Scheduling 温度相关倾斜调度的双图方法

2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-03-01 DOI: 10.1109/ISQED48828.2020.9137032

M. Kaneko

引用次数: 0

Deep Neural Network Based Speech Recognition Systems Under Noise Perturbations 噪声扰动下基于深度神经网络的语音识别系统

2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-03-01 DOI: 10.1109/ISQED48828.2020.9136978

Qiyuan An, Kangjun Bai, Moqi Zhang, Y. Yi, Yifang Liu

引用次数: 0