2020 21st International Symposium on Quality Electronic Design (ISQED)最新文献_第3页

Piezoelectric CMOS Charger: Highest Output-Power Design 压电CMOS充电器:最高输出功率设计

2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-03-01 DOI: 10.1109/ISQED48828.2020.9137018

Siyu Yang, G. Rincón-Mora

引用次数: 1

Rehabilitation System for Limbs using IMUs 使用imu的肢体康复系统

2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-03-01 DOI: 10.1109/ISQED48828.2020.9137026

Chun-Jui Chen, Yi-Ting Lin, Chia-Chun Lin, Yung-Chih Chen, Yun-Ju Lee, Chun-Yao Wang

引用次数: 6

A Scalable FPGA Engine for Parallel Acceleration of Singular Value Decomposition 一种并行加速奇异值分解的可扩展FPGA引擎

2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-03-01 DOI: 10.1109/ISQED48828.2020.9137055

Yu Wang, Jeong-Jun Lee, Yu Ding, Peng Li

引用次数: 6

Strong Anti-SAT: Secure and Effective Logic Locking 强抗sat:安全有效的逻辑锁定

2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-03-01 DOI: 10.1109/ISQED48828.2020.9136983

Yuntao Liu, Michael Zuzak, Yang Xie, Abhishek Chakraborty, Ankur Srivastava

{"title":"Strong Anti-SAT: Secure and Effective Logic Locking","authors":"Yuntao Liu, Michael Zuzak, Yang Xie, Abhishek Chakraborty, Ankur Srivastava","doi":"10.1109/ISQED48828.2020.9136983","DOIUrl":"https://doi.org/10.1109/ISQED48828.2020.9136983","url":null,"abstract":"Logic locking has been proposed as strong protection of intellectual property (IP) against security threats in the IC supply chain especially when the fabrication facility is untrusted. Such techniques use additional locking circuitry to inject incorrect behavior into the digital functionality when the key is incorrect. A family of attacks known as “SAT attacks” provides a strong mathematical formulation to find the correct key of locked circuits. Many conventional SAT-resilient logic locking schemes fail to inject sufficient error into the circuit when the key is incorrect: there are usually very few (or only one) input minterms that cause any error at the circuit output [18], [20]–[22]. The state-of-the-art stripped functionality logic locking (SFLL) [24] technique provides a wide spectrum of configurations which introduced a trade-off between security (i.e. SAT attack complexity) and effectiveness (i.e. the amount of error injected by a wrong key). In this work, we prove that such a trade-off is universal among all logic locking techniques. In order to attain high effectiveness of locking without compromising security, we propose a novel secure and effective logic locking scheme, called Strong Anti-SAT (SAS). SAS has the following significant improvements over existing techniques. (1) We prove that SAS's security against SAT attack is not compromised by increases in effectiveness. (2) In contrast to prior work which focused solely on the circuit-level locking impact, we integrate SAS-locked modules into an 80386 processor and show that SAS has a high application-level impact. (3) SAS's hardware overhead is smaller than that of existing techniques.","PeriodicalId":225828,"journal":{"name":"2020 21st International Symposium on Quality Electronic Design (ISQED)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132892228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 24

Analytical Estimation and Localization of Hardware Trojan Vulnerability in RTL Designs RTL设计中硬件木马漏洞的分析、估计与定位

2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-03-01 DOI: 10.1109/ISQED48828.2020.9137024

S. A. Islam, Love Kumar Sah, S. Katkoori

{"title":"Analytical Estimation and Localization of Hardware Trojan Vulnerability in RTL Designs","authors":"S. A. Islam, Love Kumar Sah, S. Katkoori","doi":"10.1109/ISQED48828.2020.9137024","DOIUrl":"https://doi.org/10.1109/ISQED48828.2020.9137024","url":null,"abstract":"Offshoring the proprietary Intellectual property (IP) has recently increased the threat of malicious logic insertion in the form of Hardware Trojan (HT). A potential and stealthy HT is triggered with nets that switch rarely during regular circuit operation. Detection of HT in the host design requires exhaustive simulation to activate the HT during pre- and post-silicon. Although the nets with variable switching probability less than a threshold are primarily chosen as a good candidate for Trojan triggering, there is no systematic fine-grained approach for earlier detection of rare nets from word-level measures of input signals. In this paper, we propose a high-level technique to estimate the nets with the rare activity of arithmetic modules from word-level information. Specifically, for a given module, we use the knowledge of internal construction of the architecture to detect “low activity” and “local regions” without resorting to expensive RTL and other low-level simulations. The presented heuristic method abstracts away from the low-level details of design and describes the rare activity of bits (modules) in a word (architecture) as a function of signal statistics. The resulting quick estimates of nets in rare regions allows a designer to develop a compact test generation algorithm without the knowledge of the bit-level activity. We determine the effect of different positions of the breakpoint in the input signal to calculate the accuracy of the approach. We conduct a set of experiments on six adder architectures and four multiplier architectures. The average error to calculate the rare nets between RTL simulation and estimated values are below 2% in all architectures.","PeriodicalId":225828,"journal":{"name":"2020 21st International Symposium on Quality Electronic Design (ISQED)","volume":"4 12","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131671860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Efficient Transfer Learning on Modeling Physical Unclonable Functions 物理不可克隆函数建模的高效迁移学习

2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-03-01 DOI: 10.1109/ISQED48828.2020.9137057

Qian Wang, Omid Aramoon, Pengfei Qiu, G. Qu

引用次数: 0

SeqL: Secure Scan-Locking for IP Protection SeqL: IP保护的安全扫描锁定

2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-03-01 DOI: 10.1109/ISQED48828.2020.9136991

S. Potluri, Aydin Aysu, Akash Kumar

引用次数: 14

ISQED'20 Best Papers ISQED'20最佳论文

2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-03-01 DOI: 10.1109/ISQED48828.2020.9137010

Xianwei Cheng, Hui-Qun Zhao, M. Kandemir, S. Mohanty, Beilei Jiang, Marzieh Vaeztourshizi, M. Kamal, M. Pedram, Mohammad Nasim Imtiaz Khan, Chak Yuen Cheng, Sung-Hao Lin, Abdullah Ash, Swaroop Ghosh

引用次数: 0

Two-Graph Approach to Temperature Dependent Skew Scheduling 温度相关倾斜调度的双图方法

2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-03-01 DOI: 10.1109/ISQED48828.2020.9137032

M. Kaneko

引用次数: 0

Deep Neural Network Based Speech Recognition Systems Under Noise Perturbations 噪声扰动下基于深度神经网络的语音识别系统

2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-03-01 DOI: 10.1109/ISQED48828.2020.9136978

Qiyuan An, Kangjun Bai, Moqi Zhang, Y. Yi, Yifang Liu

引用次数: 0