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2020 21st International Symposium on Quality Electronic Design (ISQED)最新文献

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EM Fault Injection on ARM and RISC-V 基于ARM和RISC-V的EM故障注入
2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-03-01 DOI: 10.1109/ISQED48828.2020.9137051
Mahmoud A. Elmohr, Haohao Liao, C. Gebotys
{"title":"EM Fault Injection on ARM and RISC-V","authors":"Mahmoud A. Elmohr, Haohao Liao, C. Gebotys","doi":"10.1109/ISQED48828.2020.9137051","DOIUrl":"https://doi.org/10.1109/ISQED48828.2020.9137051","url":null,"abstract":"Recently Electro-Magnetic Fault Injection (EMFI) techniques have been found to have significant implications on the security of embedded devices. Unfortunately, there is still a lack of understanding of EM faults and countermeasures for embedded processors. For the first time, this paper empirically shows that EMFI can cause skipping/faulting of more than one instruction on a 320MHz RISC-V processor, thus making it susceptible to a wider range of attacks. Additionally, empirical results on ARM Cortex M0 and RISC-V embedded processors show that EMFI is more susceptible at lower supply voltages and higher clock frequencies. Exception codes are also shown to be useful in understanding details of injected faults, providing further evidence that instructions have been corrupted in many cases. This research aims to enhance the understanding of faults, in order to better design countermeasures for embedded processors resistant to fault injection attacks.","PeriodicalId":225828,"journal":{"name":"2020 21st International Symposium on Quality Electronic Design (ISQED)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133227605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
NN-PARS: A Parallelized Neural Network Based Circuit Simulation Framework NN-PARS:一种基于并行神经网络的电路仿真框架
2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-02-13 DOI: 10.1109/ISQED48828.2020.9137047
M. Abrishami, Hao Ge, Justin F. Calderon, M. Pedram, Shahin Nazarian
{"title":"NN-PARS: A Parallelized Neural Network Based Circuit Simulation Framework","authors":"M. Abrishami, Hao Ge, Justin F. Calderon, M. Pedram, Shahin Nazarian","doi":"10.1109/ISQED48828.2020.9137047","DOIUrl":"https://doi.org/10.1109/ISQED48828.2020.9137047","url":null,"abstract":"The shrinking of transistor geometries as well as the increasing complexity of integrated circuits, significantly aggravate nonlinear design behavior. This demands accurate and fast circuit simulation to meet the design quality and time-to-market constraints. The existing circuit simulators which utilize lookup tables and/or closed-form expressions are either slow or inaccurate in analyzing the nonlinear behavior of designs with billions of transistors. To address these shortcomings, we present NN-PARS, a neural network (NN) based and parallelized circuit simulation framework with optimized event-driven scheduling of simulation tasks to maximize concurrency, according to the underlying GPU parallel processing capabilities. NN-PARS replaces the required memory queries in traditional techniques with parallelized NN-based computation tasks. Experimental results show that compared to a state-of-the-art current-based simulation method, NN-PARS reduces the simulation time by over two orders of magnitude in large circuits. NN-PARS also provides high accuracy levels in signal waveform calculations, with less than 2% error compared to HSPICE.","PeriodicalId":225828,"journal":{"name":"2020 21st International Symposium on Quality Electronic Design (ISQED)","volume":"329 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115968314","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Efficient Training of Deep Convolutional Neural Networks by Augmentation in Embedding Space 基于嵌入空间增强的深度卷积神经网络高效训练
2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-02-12 DOI: 10.1109/ISQED48828.2020.9137053
M. Abrishami, Amir Erfan Eshratifar, D. Eigen, Yanzhi Wang, Shahin Nazarian, M. Pedram
{"title":"Efficient Training of Deep Convolutional Neural Networks by Augmentation in Embedding Space","authors":"M. Abrishami, Amir Erfan Eshratifar, D. Eigen, Yanzhi Wang, Shahin Nazarian, M. Pedram","doi":"10.1109/ISQED48828.2020.9137053","DOIUrl":"https://doi.org/10.1109/ISQED48828.2020.9137053","url":null,"abstract":"Recent advances in the field of artificial intelligence have been made possible by deep neural networks. In applications where data are scarce, transfer learning and data augmentation techniques are commonly used to improve the generalization of deep learning models. However, fine-tuning a transfer model with data augmentation in the raw input space has a high computational cost to run the full network for every augmented input. This is particularly critical when large models are implemented on embedded devices with limited computational and energy resources. In this work, we propose a method that replaces the augmentation in the raw input space with an approximate one that acts purely in the embedding space. Our experimental results show that the proposed method drastically reduces the computation, while the accuracy of models is negligibly compromised.","PeriodicalId":225828,"journal":{"name":"2020 21st International Symposium on Quality Electronic Design (ISQED)","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116711068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
LASCA: Learning Assisted Side Channel Delay Analysis for Hardware Trojan Detection 学习辅助侧信道延迟分析硬件木马检测
2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-01-17 DOI: 10.1109/ISQED48828.2020.9137007
Ashka Vakil, F. Behnia, Ali Mirzaeian, H. Homayoun, Naghmeh Karimi, Avesta Sasan
{"title":"LASCA: Learning Assisted Side Channel Delay Analysis for Hardware Trojan Detection","authors":"Ashka Vakil, F. Behnia, Ali Mirzaeian, H. Homayoun, Naghmeh Karimi, Avesta Sasan","doi":"10.1109/ISQED48828.2020.9137007","DOIUrl":"https://doi.org/10.1109/ISQED48828.2020.9137007","url":null,"abstract":"In this paper, we introduce a Learning Assisted Side Channel delay Analysis (LASCA) methodology for Hardware Trojan detection. Our proposed solution, unlike the prior art, does not require a Golden IC. Instead, it trains a Neural Network to act as a process tracking watchdog for correlating the static timing data (produced at design time) to the delay information obtained from clock frequency sweeping (at test time) for the purpose of Trojan detection. Using the LASCA flow, we detect close to 90% of Hardware Trojans in the simulated scenarios.","PeriodicalId":225828,"journal":{"name":"2020 21st International Symposium on Quality Electronic Design (ISQED)","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129105259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Code-Bridged Classifier (CBC): A Low or Negative Overhead Defense for Making a CNN Classifier Robust Against Adversarial Attacks 代码桥接分类器(CBC):使CNN分类器对对抗性攻击具有鲁棒性的低或负开销防御
2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-01-16 DOI: 10.1109/ISQED48828.2020.9136987
F. Behnia, Ali Mirzaeian, M. Sabokrou, S. Manoj, T. Mohsenin, Khaled N. Khasawneh, Liang Zhao, H. Homayoun, Avesta Sasan
{"title":"Code-Bridged Classifier (CBC): A Low or Negative Overhead Defense for Making a CNN Classifier Robust Against Adversarial Attacks","authors":"F. Behnia, Ali Mirzaeian, M. Sabokrou, S. Manoj, T. Mohsenin, Khaled N. Khasawneh, Liang Zhao, H. Homayoun, Avesta Sasan","doi":"10.1109/ISQED48828.2020.9136987","DOIUrl":"https://doi.org/10.1109/ISQED48828.2020.9136987","url":null,"abstract":"In this paper, we propose Code-Bridged Classifier (CBC), a framework for making a Convolutional Neural Network (CNNs) robust against adversarial attacks without increasing or even by decreasing the overall models' computational complexity. More specifically, we propose a stacked encoder-convolutional model, in which the input image is first encoded by the encoder module of a denoising auto-encoder, and then the resulting latent representation (without being decoded) is fed to a reduced complexity CNN for image classification. We illustrate that this network not only is more robust to adversarial examples but also has a significantly lower computational complexity when compared to the prior art defenses.","PeriodicalId":225828,"journal":{"name":"2020 21st International Symposium on Quality Electronic Design (ISQED)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-01-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128542224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Integration and Evaluation of Quantum Accelerators for Data-Driven User Functions 数据驱动用户功能的量子加速器集成与评估
2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2019-12-12 DOI: 10.1109/ISQED48828.2020.9137029
T. Hubregtsen, Christoph Segler, Josef Pichlmeier, A. Sarkar, Thomas Gabor, K. Bertels
{"title":"Integration and Evaluation of Quantum Accelerators for Data-Driven User Functions","authors":"T. Hubregtsen, Christoph Segler, Josef Pichlmeier, A. Sarkar, Thomas Gabor, K. Bertels","doi":"10.1109/ISQED48828.2020.9137029","DOIUrl":"https://doi.org/10.1109/ISQED48828.2020.9137029","url":null,"abstract":"Quantum computers hold great promise for accelerating computationally challenging algorithms on noisy intermediate-scale quantum (NISQ) devices in the upcoming years. Much attention of the current research is directed towards algorithmic research on artificial data that is disconnected from live systems, such as optimization of systems or training of learning algorithms. In this paper we investigate the integration of quantum systems into industry-grade system architectures. In this work we propose a system architecture for the integration of quantum accelerators. In order to evaluate our proposed system architecture we investigated various data-driven functions for various accelerators, including a classical system, a gate-based quantum accelerator and a quantum annealer. The data-driven function predict user preference and is trained on real-world data. This work also includes an evaluation of the quantum enhanced kernel, that previously was only evaluated on artificial data. In our evaluation, we showed that the quantum-enhanced kernel performs at least equally well to a classical state-of-the-art kernel when simulated. We also showed a low reduction in accuracy and latency numbers within acceptable bounds when running on the gate-based IBM quantum accelerator. We therefore conclude it is feasible to integrate NISQ-era devices in industry-grade system architectures in preparation for future advancements in quantum hardware.","PeriodicalId":225828,"journal":{"name":"2020 21st International Symposium on Quality Electronic Design (ISQED)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131835082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Energy-aware Scheduling of Jobs in Heterogeneous Cluster Systems Using Deep Reinforcement Learning 基于深度强化学习的异构集群系统作业能量感知调度
2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2019-12-11 DOI: 10.1109/ISQED48828.2020.9137025
Amirhossein Esmaili, M. Pedram
{"title":"Energy-aware Scheduling of Jobs in Heterogeneous Cluster Systems Using Deep Reinforcement Learning","authors":"Amirhossein Esmaili, M. Pedram","doi":"10.1109/ISQED48828.2020.9137025","DOIUrl":"https://doi.org/10.1109/ISQED48828.2020.9137025","url":null,"abstract":"Energy consumption is one of the most critical concerns in designing computing devices, ranging from portable embedded systems to computer cluster systems. Furthermore, in the past decade, cluster systems have increasingly risen as popular platforms to run computing-intensive real-time applications in which the performance is of great importance. However, due to different characteristics of real-time workloads, developing general job scheduling solutions that efficiently address both energy consumption and performance in real-time cluster systems is a challenging problem. In this paper, inspired by recent advances in applying deep reinforcement learning for resource management problems, we present the Deep-EAS scheduler that learns efficient energy-aware scheduling strategies for workloads with different characteristics without initially knowing anything about the scheduling task at hand. Results show that Deep-EAS converges quickly, and performs better compared to standard manually-tuned heuristics, especially in heavy load conditions.","PeriodicalId":225828,"journal":{"name":"2020 21st International Symposium on Quality Electronic Design (ISQED)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124464830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Alleviating Bottlenecks for DNN Execution on GPUs via Opportunistic Computing 通过机会计算缓解gpu上DNN执行的瓶颈
2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2019-10-15 DOI: 10.1109/ISQED48828.2020.9136967
Xianwei Cheng, Hui Zhao, M. Kandemir, S. Mohanty, Beilei Jiang
{"title":"Alleviating Bottlenecks for DNN Execution on GPUs via Opportunistic Computing","authors":"Xianwei Cheng, Hui Zhao, M. Kandemir, S. Mohanty, Beilei Jiang","doi":"10.1109/ISQED48828.2020.9136967","DOIUrl":"https://doi.org/10.1109/ISQED48828.2020.9136967","url":null,"abstract":"Edge computing and IoT applications are severely constrained by limited hardware resource. This makes memory-consuming DNN (Deep Neural Network) frameworks not applicable to edge computing. Simple algorithms such as direct convolution are finding their way in embedded machine learning. As one of the most widely used platforms for DNN acceleration, GPUs face the bottleneck of on-chip bandwidth. This work introduces a GPU DNN execution architecture that can relieve the on-chip bandwidth bottleneck by reducing data movement through opportunistic computing. We first investigate data access patterns in the hardware's view. Then we propose two opportunistic computing techniques to predictably perform computation when data is available with the help of assistant warps. By moving computation to data, our techniques are able to significantly reduce data movement and relieve the DNN execution bottleneck. Our evaluation results show that the proposed technique can improve DNN application performance as much as 55%.","PeriodicalId":225828,"journal":{"name":"2020 21st International Symposium on Quality Electronic Design (ISQED)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131543176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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