2020 21st International Symposium on Quality Electronic Design (ISQED)最新文献

{"title":"SATConda: SAT to SAT-Hard Clause Translator","authors":"Rakibul Hassan, Gaurav Kolhe, S. Rafatirad, H. Homayoun, Sai Manoj Pudukotai Dinakarrao","doi":"10.1109/ISQED48828.2020.9137052","DOIUrl":"https://doi.org/10.1109/ISQED48828.2020.9137052","url":null,"abstract":"Logic obfuscation emerged as an efficient solution to strengthen the security of integrated circuits (ICs) from multiple threats including reverse engineering and intellectual property (IP) theft. Emergence of Boolean Satisfiability (SAT) attacks and its variants have shown to circumvent the security mechanisms such as obfuscation and a plethora of its variants. A plethora of advanced security defenses to thwart the SAT attacks are introduced. Despite the effectiveness, the imposed overheads in terms of area and power are unacceptably high. In contrast, our current work focuses on devising an iterative, dynamic and intelligent SAT-hard clause generator for a given SAT-prone problem, termed as SATConda. The SATConda is a SAT-hard clause generator that utilizes a bipartite propagation based neural network model. The utilized model comprises multiple layers of artificial neural networks to extract the dependencies of literals and variables, followed by long short term memory (LSTM) networks to validate the SAT hardness. The SATConda is trained with conjunctive normal form (CNF) of the IC netlist that are both SAT solvable and SAT-hard. Further, the SATConda is equipped with a SAT-clause generator to convert a CNF from satisfiable (SAT) to unsatisfiable (unSAT) with minor perturbation (which translates to minor overheads) so that the SAT-attack cannot decrypt the keys. To the best of our knowledge, no previous work has been reported on neural network based SAT-hard clause or CNF translator for circuit obfuscation. We evaluate our proposed SATConda's empirical performance against MiniSAT, Lingeling and Glucose SAT solvers on ISCAS'85 benchmark circuits.","PeriodicalId":225828,"journal":{"name":"2020 21st International Symposium on Quality Electronic Design (ISQED)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126257887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Methodology for Reusable Physical Design","authors":"Edward Wang, Colin Schmidt, Adam M. Izraelevitz, J. Wright, B. Nikolić, E. Alon, J. Bachrach","doi":"10.1109/ISQED48828.2020.9136999","DOIUrl":"https://doi.org/10.1109/ISQED48828.2020.9136999","url":null,"abstract":"Traditional physical design flows force users to intermix distinct information relating to logical design, physical design, technology, and tool concerns during chip implementation, leading to high design effort, costs, and time-to-market. We introduce Hammer, a physical design generator which remedies these problems via separation of concerns. Through its modular software architecture, Hammer is able to separate tool and technology concerns, while Hammer's data format separates logical and physical design concerns, enabling physical design information to be generated in sync with changes to the logical design. We evaluate Hammer's flexibility and effective software architecture by demonstrating wide-ranging reductions in time, cost, and design effort in various physical design tasks through multiple tapeouts using multiple technologies (ranging from 45nm to 16nm), tools, and design architectures.","PeriodicalId":225828,"journal":{"name":"2020 21st International Symposium on Quality Electronic Design (ISQED)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129031495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design Space Exploration Driven by Lifetime Concerns due to Electromigration","authors":"F. Wolff, D. Weyer, C. Papachristou, Steve Clay","doi":"10.1109/ISQED48828.2020.9137040","DOIUrl":"https://doi.org/10.1109/ISQED48828.2020.9137040","url":null,"abstract":"Lifetime has not been a significant factor or primary concern in the integrated circuit (IC) design cycle of past process nodes. Lifetime was typically pushed at the end of the design process as signoff. If the electromigration rules weren't violated, lifetime was deemed acceptable. This viewpoint is shifting, from what is allowed, to what the IC mission profile needs. A designer needs to know how much, more or less, lifetime tradeoff with performance, power and cost can be achieved within the mission profile constraints. This paper describes a design space exploration methodology that moves electromigration lifetime tradeoffs early into the design cycle, without the need to re-characterize the process, while working with the existing technology library.","PeriodicalId":225828,"journal":{"name":"2020 21st International Symposium on Quality Electronic Design (ISQED)","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134526151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Optimal Choice of Waveform for Library Characterization for Accurate Delay Calculation","authors":"Ajoy Mandal, Saili Shete","doi":"10.1109/ISQED48828.2020.9137033","DOIUrl":"https://doi.org/10.1109/ISQED48828.2020.9137033","url":null,"abstract":"Accuracy of waveform aware delay calculation approaches in STA tools require selection of an appropriate driver waveform during library characterization. The optimal waveform shape is dependent on process corner, voltage, temperature, parasitics and also the properties of the transistors involved. Traditionally used ramp waveform is not suitable for accuracy particularly at lower voltages and temperatures. Identification of waveform shape across a wide range of operating corners and for different transistor types can involve significant cost in terms of resources and time. This paper discusses an efficient approach for finding the driver waveform for library characterization. It also enlists the factors that influence the waveform shape and the related careabouts during the waveform identification process. Lastly, it proposes an approach to reduce the run-time and resources used to get the optimal characterization waveform at all operating corners.","PeriodicalId":225828,"journal":{"name":"2020 21st International Symposium on Quality Electronic Design (ISQED)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116609578","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Highest Wireless Power: Inductively Coupled Or RF?","authors":"N. Xing, G. Rincón-Mora","doi":"10.1109/ISQED48828.2020.9136990","DOIUrl":"https://doi.org/10.1109/ISQED48828.2020.9136990","url":null,"abstract":"Embedded microsensors are the critical components for the Internet of Things (IoT) as they provide interfaces between the physical and the digital worlds. Unfortunately, these microsensors' tiny batteries cannot sustain their operation for long. Ambient energy sources, such as light or motion, are not always available, so transmitting power wirelessly is often the only option to recharge their onboard batteries. This paper discusses and compares two of the most popular wireless power transfer technologies: inductively coupled and RF, in terms of their highest output power over distance. As an example, a 125 kHz, coil-based inductively coupled power transfer system is compared with a 2.45 GHz, antenna-based RF power transfer system. When closely coupled, the inductively coupled receiver outputs higher power density with a normalized transmitter. As the distance grows, the power density of the inductively coupled receiver decays 3 times faster than the RF. So past 3.5 times of the transmitter's length, the RF's power density beats the inductively coupled.","PeriodicalId":225828,"journal":{"name":"2020 21st International Symposium on Quality Electronic Design (ISQED)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128063912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Insulator-Metal Transition Material Based Artificial Neurons: A Design Perspective","authors":"A. Aziz, K. Roy","doi":"10.1109/ISQED48828.2020.9136994","DOIUrl":"https://doi.org/10.1109/ISQED48828.2020.9136994","url":null,"abstract":"We analyze the dynamics of insulator-metal transition (IMT) based neurons, through material-device co-design and optimization. We explore the correlation between the membrane potential and the bias voltage for the resistance stack of the IMT neuron. For a set of nominal parameters, we show that a minimum bias voltage of ~300 mV and a minimum gate input of ~400 mV is required to ensure oscillatory behavior in the IMT neuron. These biasing constraints can be slightly relaxed by increasing the size of the auxiliary transistor. A 4X increase in the transistor width can only lead to ~ 80 mV increase in the window of oscillatory operation with a ~3.8X increase in the current through the neuron. For low power operation, it is optimum to use minimum sized transistor with more than 400 mV of membrane and bias voltages. Analyzing the implications of the material parameters, we report that, the trigger voltage $(V_{TRIG})$ of the neuron can be linearly tuned by choosing appropriate critical voltage for IMT switching. The insulating state resistance $(R_{INS})$ also plays a role in determining the $V_{TRIG}$. But, to reduce the $V_{TRIG}$ by 50 mV, the $R_{INS}$ needs to be lowered by ~5X. For $R_{INS} < 150mathrm{K}Omega$ and metallic state resistance $(RMET) < 700Omega$, it is possible to operate the neuron in a special bi-stable oscillatory mode (avoiding the metastable operation). But if the width of transistor is lower $(N_{FIN} < 4)$, only metastable oscillation is possible. The frequency of oscillation is coupled to the transistor resistance and ~25 mV reduction in threshold voltage $(V_{TH})$ leads to $> 15%$ increase in the frequency. We perform 10,000 Monte-Carlo simulations $(3sigma)$ to analyze the effect of variation on this neuron topology. Considering Gaussian distribution in the $V_{TH}$ and in all the parameters of the IMT material, we calculate ~150 mV of spread in the values of the $V_{TRIG}$ The variation induced spread is not sensitive to the transistor size. That indicates the possibility of using a minimum sized transistor, without affecting the degree of variation tolerance of the neuron.","PeriodicalId":225828,"journal":{"name":"2020 21st International Symposium on Quality Electronic Design (ISQED)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128926608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Survey on Neural Trojans","authors":"Yuntao Liu, Ankit Mondal, Abhishek Chakraborty, Michael Zuzak, Nina L. Jacobsen, Daniel Xing, Ankur Srivastava","doi":"10.1109/ISQED48828.2020.9137011","DOIUrl":"https://doi.org/10.1109/ISQED48828.2020.9137011","url":null,"abstract":"Neural networks have become increasingly prevalent in many real-world applications including security critical ones. Due to the high hardware requirement and time consumption to train high-performance neural network models, users often outsource training to a machine-learning-as-a-service (MLaaS) provider. This puts the integrity of the trained model at risk. In 2017, Liu et al. found that, by mixing the training data with a few malicious samples of a certain trigger pattern, hidden functionality can be embedded in the trained network which can be evoked by the trigger pattern [33]. We refer to this kind of hidden malicious functionality as neural Trojans. In this paper, we survey a myriad of neural Trojan attack and defense techniques that have been proposed over the last few years. In a neural Trojan insertion attack, the attacker can be the MLaaS provider itself or a third party capable of adding or tampering with training data. In most research on attacks, the attacker selects the Trojan's functionality and a set of input patterns that will trigger the Trojan. Training data poisoning is the most common way to make the neural network acquire the Trojan functionality. Trojan embedding methods that modify the training algorithm or directly interfere with the neural network's execution at the binary level have also been studied. Defense techniques include detecting neural Trojans in the model and/or Trojan trigger patterns, erasing the Trojan's functionality from the neural network model, and bypassing the Trojan. It was also shown that carefully crafted neural Trojans can be used to mitigate other types of attacks. We systematize the above attack and defense approaches in this paper.","PeriodicalId":225828,"journal":{"name":"2020 21st International Symposium on Quality Electronic Design (ISQED)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132321165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An NBTI-aware Task Parallelism Scheme for Improving Lifespan of Multi-core Systems","authors":"Yu-Guang Chen, Yu-Yi Lin, Ing-Chao Lin","doi":"10.1109/ISQED48828.2020.9137005","DOIUrl":"https://doi.org/10.1109/ISQED48828.2020.9137005","url":null,"abstract":"Task parallelism schemes with a multi-core system are widely used through various applications nowadays to obtain better throughput. Most of previous works will try to find maximum degree of parallelism (DOP) to achieve best performance. However, aging effects have become an unavoidable threat which may degrade system performance and even cause functional failure. We observe that if a task is always executed with maximum DOP, all cores may continuously suffer from the NBTI effect and wear out soon. On the other hand, if we can decrease DOP without causing task deadline violation, some cores may have opportunities to be power-gated and recover from the NBTI effect. In this paper, we propose a novel NBTI-aware task parallelism framework for multi-core systems to realize such an idea. Our framework first prioritizes ready tasks based on its criticality and then decide best DOP of each task without causing timing violation. After that, a task-to-core mapping algorithm which considers both IR-drop and core utilization is proposed. Finally, a recover decision algorithm is used to find the suitable recover mode of each core. Experimental results show that the proposed NBTI-aware task parallelism framework can successfully extend system lifetime to 3.7 times compared with MAX DOP method.","PeriodicalId":225828,"journal":{"name":"2020 21st International Symposium on Quality Electronic Design (ISQED)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126353078","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Compression or Corruption? A Study on the Effects of Transient Faults on BNN Inference Accelerators","authors":"N. Khoshavi, Connor Broyles, Yu Bi","doi":"10.1109/ISQED48828.2020.9137006","DOIUrl":"https://doi.org/10.1109/ISQED48828.2020.9137006","url":null,"abstract":"Over past years, the philosophy for designing the artificial intelligence algorithms has significantly shifted towards automatically extracting the composable systems from massive data volumes. This paradigm shift has been expedited by the big data booming which enables us to easily access and analyze the highly large data sets. The most well-known class of big data analysis techniques is called deep learning. These models require significant computation power and extremely high memory accesses which necessitate the design of novel approaches to reduce the memory access and improve power efficiency while taking into account the development of domain-specific hardware accelerators to support the current and future data sizes and model structures. The current trends for designing application-specific integrated circuits barely consider the essential requirement for maintaining the complex neural network computation to be resilient in the presence of soft errors. The soft errors might strike either memory storage or combinational logic in the hardware accelerator that can affect the architectural behavior such that the precision of the results fall behind the minimum allowable correctness. In this study, we demonstrate that the impact of soft errors on a customized deep learning algorithm called Binarized Neural Network might cause drastic image misclassification. Our experimental results show that the accuracy of image classifier can drastically drop by 76.70% and 19.25% in IfcW1A1 and cnvW1A1 networks, respectively across CIFAR-10 and MNIST datasets during the fault injection for the worst-case scenarios.","PeriodicalId":225828,"journal":{"name":"2020 21st International Symposium on Quality Electronic Design (ISQED)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126411265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Low-Power LSTM Processor for Multi-Channel Brain EEG Artifact Detection","authors":"Hasib-Al Rashid, N. Manjunath, Hirenkumar Paneliya, M. Hosseini, W. Hairston, T. Mohsenin","doi":"10.1109/ISQED48828.2020.9137056","DOIUrl":"https://doi.org/10.1109/ISQED48828.2020.9137056","url":null,"abstract":"This paper proposes a low complexity Long Short-Term Memory (LSTM) based neural network architecture for detecting various artifacts in multi-channel brain EEG signals. Our proposed method consists of one average pooling layer of size 64, one LSTM layer having 12 units, one dense layer having 50 neurons and one output layer for binary classification. Our proposed method obtains average binary artifact detection accuracy of 93.1% which outperforms previous techniques based on Convolutional Neural Network (CNN) and Auto Regressive (AR) models for artifact detection in terms of binary classification accuracy. A complete hardware solution based on the proposed LSTM processor is designed in Verilog HDL, synthesized, and placed-and-routed on Artix- 7 FPGA which consumes 17 mW power at operating frequency of 52.6 MHz. The proposed design is also implemented on NVIDIA Jetson TX2 platform. The experimental results indicate that our FPGA implementation outperforms the most efficient configuration of the ARM CPU by 13.5 × in terms of power consumption. Compared to a previous work, our LSTM based FPGA hardware outperforms the CNN based FPGA hardware by 1.88× in terms of dynamic power consumption per classification.","PeriodicalId":225828,"journal":{"name":"2020 21st International Symposium on Quality Electronic Design (ISQED)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127741429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}