NN-PARS: A Parallelized Neural Network Based Circuit Simulation Framework

M. Abrishami, Hao Ge, Justin F. Calderon, M. Pedram, Shahin Nazarian
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引用次数: 1

Abstract

The shrinking of transistor geometries as well as the increasing complexity of integrated circuits, significantly aggravate nonlinear design behavior. This demands accurate and fast circuit simulation to meet the design quality and time-to-market constraints. The existing circuit simulators which utilize lookup tables and/or closed-form expressions are either slow or inaccurate in analyzing the nonlinear behavior of designs with billions of transistors. To address these shortcomings, we present NN-PARS, a neural network (NN) based and parallelized circuit simulation framework with optimized event-driven scheduling of simulation tasks to maximize concurrency, according to the underlying GPU parallel processing capabilities. NN-PARS replaces the required memory queries in traditional techniques with parallelized NN-based computation tasks. Experimental results show that compared to a state-of-the-art current-based simulation method, NN-PARS reduces the simulation time by over two orders of magnitude in large circuits. NN-PARS also provides high accuracy levels in signal waveform calculations, with less than 2% error compared to HSPICE.
NN-PARS:一种基于并行神经网络的电路仿真框架
晶体管几何形状的缩小以及集成电路的复杂性的增加,极大地加剧了非线性设计行为。这需要精确和快速的电路仿真,以满足设计质量和上市时间的限制。现有的电路模拟器使用查找表和/或封闭形式的表达式,在分析具有数十亿晶体管的设计的非线性行为时要么缓慢要么不准确。为了解决这些缺点,我们提出了NN- pars,这是一个基于神经网络(NN)的并行电路仿真框架,根据底层GPU并行处理能力,优化了仿真任务的事件驱动调度,以最大限度地提高并发性。NN-PARS用基于神经网络的并行计算任务取代了传统技术中所需的内存查询。实验结果表明,与目前最先进的基于电流的仿真方法相比,NN-PARS在大型电路中的仿真时间缩短了两个数量级以上。NN-PARS在信号波形计算方面也提供了高精度水平,与HSPICE相比误差小于2%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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