2020 21st International Symposium on Quality Electronic Design (ISQED)最新文献_第5页

FeFET-Based Neuromorphic Architecture with On-Device Feedback Alignment Training 基于效应场效应的神经形态结构与设备上反馈校准训练

2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-03-01 DOI: 10.1109/ISQED48828.2020.9137035

Sumin Jot, Abdullah M. Zyarah, S. Kurinec, K. Ni, F. Zohora, D. Kudithipudi

引用次数: 0

Diagnostic Circuit for Latent Fault Detection in SRAM Row Decoder SRAM行解码器潜在故障检测诊断电路

2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-03-01 DOI: 10.1109/ISQED48828.2020.9136968

S. Singh, Varshita Gupta, Anuj Grover, Kedar Janardhan Dhori

{"title":"Diagnostic Circuit for Latent Fault Detection in SRAM Row Decoder","authors":"S. Singh, Varshita Gupta, Anuj Grover, Kedar Janardhan Dhori","doi":"10.1109/ISQED48828.2020.9136968","DOIUrl":"https://doi.org/10.1109/ISQED48828.2020.9136968","url":null,"abstract":"Functional safety is crucial in automotive life-critical systems. Early diagnosis of unanticipated faults and failures is necessary to prevent hazardous implications. ISO 26262, Functional Safety-Road Vehicles, is an automotive industry-specific functional safety standard that describes the course for classification, detection and control of potential risks. Electromigration induced open and short defects and Bias Temperature Instability (BTI) are critical failure mechanisms and pose severe reliability concerns as they may escape tests at fabrication and cause failures when the chip eventually wears out. This paper analyzes the independent and combined impact of partial resistive defects and BTI on row decoders at 55nm technology node. The presence of resistive defects causes an additional delay which gets further increased due to aging (BTI). Due to the combined impact of 10 years of aging and a $25mathrm{K}Omega$ resistive defect, the activation delay increases by about 16.15% and the deactivation delay increases by about 22.14%. A novel technology-agnostic diagnostic test circuit and method is proposed to detect small resistive defects as low as $5mathrm{K}Omega$ before they can result in functional failure.","PeriodicalId":225828,"journal":{"name":"2020 21st International Symposium on Quality Electronic Design (ISQED)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124081931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Rethinking FPGA Security in the New Era of Artificial Intelligence 人工智能新时代对FPGA安全性的再思考

2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-03-01 DOI: 10.1109/ISQED48828.2020.9136974

Xiaolin Xu, Jiliang Zhang

{"title":"Rethinking FPGA Security in the New Era of Artificial Intelligence","authors":"Xiaolin Xu, Jiliang Zhang","doi":"10.1109/ISQED48828.2020.9136974","DOIUrl":"https://doi.org/10.1109/ISQED48828.2020.9136974","url":null,"abstract":"With various possible attacks against commercial electronic devices reported over the past few decades, the security of hardware devices and systems has become an urgent problem. Accordingly, a large number of solutions and countermeasures have been explored to mitigate these attacks. Artificial intelligence, as one of the fastest-growing research areas, also makes a unique impact on the landscape of vulnerabilities and countermeasures of hardware. As a vital subset of artificial intelligence, machine learning algorithms are found of great use in hardware security from both constructive and destructive perspectives. In this paper, we provide a survey of such double-edged sword impact of machine learning techniques on the security of hardware. In particular, we focus on the discussion of FPGA security. We enumerate both countermeasures and attacks based on pure machine learning algorithms, as well as the integration of machine learning and other methods, such as side-channel analysis. In addition, we also discuss the security concerns of FPGAs when they are used as carriers or accelerators for machine learning algorithms. Specifically, we present the security issues of FPGAs in two different application scenarios: 1) as a standalone computing resource and 2) as a public-leased computing resource shared by multiple users.","PeriodicalId":225828,"journal":{"name":"2020 21st International Symposium on Quality Electronic Design (ISQED)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125358488","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Proceedings of the Twentyfirst International Symposium on Quality Electronic Design 第21届质量电子设计国际研讨会论文集

2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-03-01 DOI: 10.1109/isqed48828.2020.9137028

引用次数: 0

[Copyright notice] (版权)

2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-03-01 DOI: 10.1109/isqed48828.2020.9137048

引用次数: 0

Extracting Power Signature from Low Dropout Voltage Regulator for IoT Security 基于物联网安全的低压稳压器功率特征提取

2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-03-01 DOI: 10.1109/ISQED48828.2020.9136971

D. Thompson, Haibo Wang

引用次数: 0

Accurate Estimation of Dynamic Timing Slacks using Event-Driven Simulation 基于事件驱动仿真的动态时序松弛精确估计

2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-03-01 DOI: 10.1109/ISQED48828.2020.9137017

Dimitrios Garyfallou, Ioannis Tsiokanos, N. Evmorfopoulos, G. Stamoulis, G. Karakonstantis

{"title":"Accurate Estimation of Dynamic Timing Slacks using Event-Driven Simulation","authors":"Dimitrios Garyfallou, Ioannis Tsiokanos, N. Evmorfopoulos, G. Stamoulis, G. Karakonstantis","doi":"10.1109/ISQED48828.2020.9137017","DOIUrl":"https://doi.org/10.1109/ISQED48828.2020.9137017","url":null,"abstract":"The pessimistic nature of conventional static timing analysis has turned the attention of many studies to the exploitation of the dynamic data-dependent excitation of paths. Such studies may have revealed extensive dynamic timing slacks (DTS), however, they rely on frameworks that inherently make worst-case assumptions and still ignore some data-dependent timing properties. This may cause significant DTS underestimation, leading to unexploited frequency scaling margins and incorrect timing failure estimation. In this paper, we develop a framework based on event-driven timing simulation that identifies the underestimated DTS, and evaluate its gains on various post-place-and-route designs. Experimental results show that our event-driven simulation scheme achieves on average 2.35% and up-to 194.51% DTS improvement over conventional graph-based techniques. When compared to existing frequency scaling schemes, the proposed approach enables us to further increase the clock frequency by up-to 10.42%. We also demonstrate that our approach can reveal that timing failures may be up-to $mathbf{2.94}times$ less than the ones estimated by existing failure estimation techniques, under potential variation-induced delay increase.","PeriodicalId":225828,"journal":{"name":"2020 21st International Symposium on Quality Electronic Design (ISQED)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123950614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Multi-Bit Read and Write Methodologies for Diode-MTJ Crossbar Array 二极管- mtj交叉棒阵列的多比特读写方法

2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-03-01 DOI: 10.1109/ISQED48828.2020.9137015

Mohammad Nasim Imtiaz Khan, Swaroop Ghosh

引用次数: 0

On Securing Scan Obfuscation Strategies Against ScanSAT Attack 针对扫描扫描攻击的安全扫描混淆策略研究

2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-03-01 DOI: 10.1109/ISQED48828.2020.9137003

R. Karmakar, S. Chattopadhyay

引用次数: 4

ISQED'20 Organizing Committee ISQED'20组委会

2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-03-01 DOI: 10.1109/isqed48828.2020.9137045

引用次数: 0