2020 21st International Symposium on Quality Electronic Design (ISQED)最新文献_第6页

Low-power Accuracy-configurable Carry Look-ahead Adder Based on Voltage Overscaling Technique 基于电压过标技术的低功耗精度可配置进位前置加法器

2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-03-01 DOI: 10.1109/ISQED48828.2020.9137039

H. Afzali-Kusha, M. Kamal, M. Pedram

{"title":"Low-power Accuracy-configurable Carry Look-ahead Adder Based on Voltage Overscaling Technique","authors":"H. Afzali-Kusha, M. Kamal, M. Pedram","doi":"10.1109/ISQED48828.2020.9137039","DOIUrl":"https://doi.org/10.1109/ISQED48828.2020.9137039","url":null,"abstract":"In this paper, a low-power accuracy-configurable block-based Carry Look-ahead Adder (AC-CLA) is proposed. The structure employs the voltage over scaling and number of approximate blocks as the approximation knobs for improving the energy consumption as well as the reliability and lifetime of the adder. While the former may be set in the design time as well as the runtime, the latter may only be invoked in the design time. In this adder, for a given accuracy level, some of the blocks work in the approximate mode by using over-scaled voltages. The block-based structure enables applying the overscaled voltage for each block independently. The efficacy of the adder depends on the number of the approximate blocks as well as the VOS voltage levels used for these blocks. The use of lower VOS voltage levels for the blocks responsible for lower significant bits which have higher switching activities is the key for reducing the power consumption of the adder while having the error within a tolerable limit. The structure requires few level shifters making the realization overhead low. The efficiency of the AC-CLA structure is studied using a 15 nm FinFET technology. The results of the study indicate that in the approximate mode up to 57% energy saving may be achieved. In addition, for this adder, the BTI induced delay degradation of the adder over 10 years decreases by up to 7% compared to 50% in the case of the exact operating mode. Finally, the efficacy of AC-CLA adder is assessed in a neural network for the classification application.","PeriodicalId":225828,"journal":{"name":"2020 21st International Symposium on Quality Electronic Design (ISQED)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133061475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Impacts of Machine Learning on Counterfeit IC Detection and Avoidance Techniques 机器学习对假冒集成电路检测和规避技术的影响

2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-03-01 DOI: 10.1109/ISQED48828.2020.9136972

Omid Aramoon, G. Qu

引用次数: 4

Error Coverage, Reliability and Cost Analysis of Fault Tolerance Techniques for 32-bit Memories used on Space Missions 空间任务用32位存储器容错技术的错误覆盖、可靠性和成本分析

2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-03-01 DOI: 10.1109/ISQED48828.2020.9137019

David C. C. Freitas, David F. M. Mota, Daniel Simões, Clailton Lopes, R. Goerl, C. Marcon, J. Silveira, J. Mota

引用次数: 0

TS-EFA: Resource-efficient High-precision Approximation of Exponential Functions Based on Template-scaling Method TS-EFA:基于模板缩放法的指数函数资源高效高精度逼近

2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-03-01 DOI: 10.1109/ISQED48828.2020.9137012

Jeeson Kim, V. Kornijcuk, D. Jeong

{"title":"TS-EFA: Resource-efficient High-precision Approximation of Exponential Functions Based on Template-scaling Method","authors":"Jeeson Kim, V. Kornijcuk, D. Jeong","doi":"10.1109/ISQED48828.2020.9137012","DOIUrl":"https://doi.org/10.1109/ISQED48828.2020.9137012","url":null,"abstract":"Spiking neural network (SNN) utilizes a number of temporal kernels that follow exponential functions with characteristic time-constants $tau$. The digital-hardware implementation of SNN-referred to as digital neuromorphic processor-suffers from the heavy workload caused by the exponential function approximation. The challenge is to reconcile the approximation accuracy with hardware resource cost optimally. To this end, we propose an exponential function approximation (EFA) method that reconciles its approximation precision with circuit overhead and calculation speed. This EFA is based on a template-scaling (TS) method; a segment of a full exponential function is taken as a template, and the template is repeatedly scaled to approximate the entire function. Therefore, we refer to our EFA as TS-EFA. The TS-EFA needs two lookup tables (LUT): template and scaling LUTs. The former is allocated to the template, whereas the latter is allocated to the scaling factors for the total bins. For experimental verification, we implemented the TS-EFA in a Xilinx Virtex-7 field-programmable gate array at 500 MHz clock speed. Two types of TS-EFA modules were considered: (i) module with a single time-constant and (ii) multiple time-constants. The module (i) successfully approximates the exponential function with a maximum absolute error of $1.3times 10^{-5}$ and a latency of four clock cycles. The module (ii) can be shared among different temporal kernels with different time-constants unlike the module (i). This module performs the approximation with the identical precision but an additional latency of four clock cycles, i.e., total eight clock cycles.","PeriodicalId":225828,"journal":{"name":"2020 21st International Symposium on Quality Electronic Design (ISQED)","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115657323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

A Layout-Based Soft Error Rate Estimation and Mitigation in the Presence of Multiple Transient Faults in Combinational Logic 组合逻辑中多暂态故障时基于布局的软错误率估计与降低

2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-03-01 DOI: 10.1109/ISQED48828.2020.9137014

C. Georgakidis, G. Paliaroutis, Nikolaos Sketopoulos, Pelopidas Tsoumanis, C. Sotiriou, N. Evmorfopoulos, G. Stamoulis

{"title":"A Layout-Based Soft Error Rate Estimation and Mitigation in the Presence of Multiple Transient Faults in Combinational Logic","authors":"C. Georgakidis, G. Paliaroutis, Nikolaos Sketopoulos, Pelopidas Tsoumanis, C. Sotiriou, N. Evmorfopoulos, G. Stamoulis","doi":"10.1109/ISQED48828.2020.9137014","DOIUrl":"https://doi.org/10.1109/ISQED48828.2020.9137014","url":null,"abstract":"Cosmic radiation resulting in transient faults to the combinational logic of Integrated Circuits (ICs), constitutes a major reliability concern for space applications. In addition, continuous technology shrinking allows for the presence of Single-Event-Multiple-Transients (SEMTs), and renders modern chips more susceptible to soft errors. The study and evaluation of the impact of such errors on ICs functionality, as well as the pursuit of techniques to mitigate Soft Error Rate (SER), tend to become an essential part of the design process. This paper presents a Monte-Carlo-based SER estimation method, taking into account all masking mechanisms, which determines the vulnerable areas of a circuit based on layout information. Two layout-aware approaches are examined, the All-to-All and TMR-based, resulting in sufficient SER mitigation. The former, implies spacing among all components, while the latter converts the most sensitive components to a TMR structure, guaranteeing spacing between TMR triplet. The TMR-based approach leads to better SER mitigation compared to All-to-All, and produces better area and performance results.","PeriodicalId":225828,"journal":{"name":"2020 21st International Symposium on Quality Electronic Design (ISQED)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129610003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

A Statistical Methodology for Post-Fabrication Weight Tuning in a Binary Perceptron 二值感知机加工后权值调整的统计方法

2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-03-01 DOI: 10.1109/ISQED48828.2020.9136979

E. Azari, Ankit Wagle, S. Khatri, S. Vrudhula

引用次数: 0

Statistical Analysis of Temperature Variability on the Write Efficiency of Spin-Orbit Torque MRAM using Polynomial Chaos Metamodels 基于多项式混沌元模型的温度变化对自旋-轨道转矩MRAM写入效率的统计分析

2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-03-01 DOI: 10.1109/ISQED48828.2020.9137004

S. Shreya, Surila Guglani, B. Kaushik, Sourajeet Roy

引用次数: 1

Vulnerability-aware Dynamic Reconfiguration of Partially Protected Caches 部分保护缓存的漏洞感知动态重配置

2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-03-01 DOI: 10.1109/ISQED48828.2020.9137050

Yuanwen Huang, P. Mishra

引用次数: 2

Energy-Efficient Edge Detection using Approximate Ramanujan Sums 基于近似拉马努金和的高效边缘检测

2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-03-01 DOI: 10.1109/ISQED48828.2020.9137002

A. Ghosh, K. Kumar, Debaprasad De, Arnab Raha, M. K. Naskar

引用次数: 3

Formal Verification of a Fully Automated Out-of-Plane Cell Injection System 全自动面外细胞注射系统的正式验证

2020 21st International Symposium on Quality Electronic Design (ISQED) Pub Date : 2020-03-01 DOI: 10.1109/ISQED48828.2020.9137036

Iram Tariq Bhatti, O. Hasan

引用次数: 0