Error Coverage, Reliability and Cost Analysis of Fault Tolerance Techniques for 32-bit Memories used on Space Missions

As the supply voltage decreases, the sensitivity of the integrated circuits to radiation increases dramatically, affecting various components such as memory cells. This paper presents, implements, and discusses seven Error Correction Code (ECC) configurations for use in 32-bit memories designed for space missions. We evaluated the proposed ECC configurations injecting two sets of faults: (i) adjacent bitflips and (ii) all possible combinations in 32-bit memory up to five bitflips. The adjacent bitflips evaluation shows that Triple Modular Redundancy with Interleaving reaches the highest correction rates, except for three and four bitflips, and the Hamming code with interleaving obtained the highest reliability. Furthermore, the evaluation of all possible combinations in a 32-bit memory shows that Reed-Muller code outperformed all other ECCs by up to three upsets and had the best reliability of all.