1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)最新文献_第4页

The channeled-BSG: a universal floorplan for simultaneous place/route with IC applications 通道式bsg:与IC应用同时放置/路由的通用平面图

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) Pub Date : 1998-11-01 DOI: 10.1145/288548.289064

S. Nakatake, K. Sakanushi, Y. Kajitani, M. Kawakita

引用次数: 23

Analysis of watermarking techniques for graph coloring problem 图形着色问题的水印技术分析

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) Pub Date : 1998-11-01 DOI: 10.1145/288548.288607

Gang Qu, M. Potkonjak

引用次数: 131

Proposal of a timing model for CMOS logic gates driving a CRC /spl pi/ load CMOS逻辑门驱动CRC /spl pi/负载的时序模型的提出

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) Pub Date : 1998-11-01 DOI: 10.1145/288548.289083

A. Hirata, H. Onodera, K. Tamaru

引用次数: 20

Control generation for embedded systems based on composition of modal processes 基于模态过程组合的嵌入式系统控制生成

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) Pub Date : 1998-11-01 DOI: 10.1145/288548.288559

Pai H. Chou, Ken Hines, K. Partridge, G. Borriello

引用次数: 10

Removal of memory access bottlenecks for scheduling control-flow intensive behavioral descriptions 消除了调度控制流密集型行为描述的内存访问瓶颈

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) Pub Date : 1998-11-01 DOI: 10.1145/288548.289089

S. Ravi, G. Lakshminarayana, N. Jha

{"title":"Removal of memory access bottlenecks for scheduling control-flow intensive behavioral descriptions","authors":"S. Ravi, G. Lakshminarayana, N. Jha","doi":"10.1145/288548.289089","DOIUrl":"https://doi.org/10.1145/288548.289089","url":null,"abstract":"Application domains like signal and image processing, multimedia and networking protocols involve processing of huge amounts of data stored in memory modules. The behavioral descriptions of these applications may contain a large number of array references for data accesses. Dependencies between array accesses cause bottlenecks in the derivation of high performance schedules. We introduce a scheduling integrated technique to identify and remove these bottlenecks. We first demonstrate that there is a significant loss in the quality of a scheduler if these bottlenecks are not taken into account by the scheduler. We then propose a technique to overcome these bottlenecks by introducing new operations in the schedule called verification operations. Experimental results on several benchmarks show that a scheduler. powered by our technique demonstrates a two fold improvement in performance (measured in terms of the average number of clock cycles) over a recently introduced scheduler for control flow intensive behavioral descriptions, called Wavesched. Wavesched itself has a two fold performance advantage over traditional methods such as path based scheduling and loop directed scheduling. Also, the best- and worst-case execution times for the enhanced schedules obtained by our method are usually equal to or much less than the corresponding values for the execution times obtained by previous schedulers.","PeriodicalId":224802,"journal":{"name":"1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133724435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Symbolic model checking of process networks using interval diagram techniques 用区间图技术进行过程网络的符号模型检验

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) Pub Date : 1998-11-01 DOI: 10.1145/288548.289117

Karsten Strehl, Lothar Thiele

引用次数: 50

Synthesis of BIST hardware for performance testing of MCM interconnections 用于MCM互连性能测试的BIST硬件的合成

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) Pub Date : 1998-11-01 DOI: 10.1145/288548.288562

R. Pendurkar, A. Chatterjee, Y. Zorian

{"title":"Synthesis of BIST hardware for performance testing of MCM interconnections","authors":"R. Pendurkar, A. Chatterjee, Y. Zorian","doi":"10.1145/288548.288562","DOIUrl":"https://doi.org/10.1145/288548.288562","url":null,"abstract":"The issue of performance testing of MCM interconnections is becoming very important due to the fact that hitherto \"second order\" effects such as ground bounce, crosstalk and switching noise are playing dominant roles in current design methods due to shrinking dimensions, lower supply voltages, higher clock speeds and higher density packaging. We propose a novel scheme for synthesizing nonlinear feedback shift register structures that can be superimposed on the boundary scan cells of ICs to generate MCM interconnect switching activities that resemble real life interconnect switching profiles. The goal is to perform at speed MCM interconnect test while simultaneously capturing the dynamic switching effects referred to earlier as accurately as possible during interconnect BIST. A library of nonlinear feedback shift register structures called Precharacterized Test Pattern Generators (P-TPG) is constructed. Components of P-TPGs are interconnected together in specific ways to recreate the switching activity profile of the interconnections being tested. An optimization algorithm for matching the P-TPG component activity profiles with those of the interconnections under test has been designed, and implemented experimental results confirm the validity of our approach.","PeriodicalId":224802,"journal":{"name":"1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133219315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

An efficient DC root solving algorithm with guaranteed convergence for analog integrated CMOS circuits 模拟集成CMOS电路中一种保证收敛的高效直流解根算法

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) Pub Date : 1998-11-01 DOI: 10.1145/288548.288629

F. Leyn, G. Gielen, W. Sansen

引用次数: 44

Hardware/software co-synthesis with memory hierarchies 与内存层次结构的硬件/软件协同合成

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) Pub Date : 1998-11-01 DOI: 10.1145/288548.289066

Yanbing Li, W. Wolf

引用次数: 61

GPCAD: a tool for CMOS op-amp synthesis GPCAD: CMOS运算放大器合成工具

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) Pub Date : 1998-11-01 DOI: 10.1145/288548.288628

M. del Mar Hershenson, Stephen P. Boyd, T. Lee

引用次数: 166