S. Nakatake, K. Sakanushi, Y. Kajitani, M. Kawakita
{"title":"通道式bsg:与IC应用同时放置/路由的通用平面图","authors":"S. Nakatake, K. Sakanushi, Y. Kajitani, M. Kawakita","doi":"10.1145/288548.289064","DOIUrl":null,"url":null,"abstract":"The BSG based packing of rectangles has been shown a breakthrough in problem size and generality, if routing is not involved. In order to include the routing, we define the channeled-BSG by associating the BSG-segs with channels. On the channeled-BSG, a new operation, flip, transforms an initial routing to another. Together with a formula that estimates the worst case width of channels for a given global routing, a solution space of simultaneous placement and routing is realized. It is proved that the space contains an optimal solution within the framework of the model. To search the space for a better solution, simulated annealing is implemented. Experiments to industrial data of analog LSIs showed a promising performance.","PeriodicalId":224802,"journal":{"name":"1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"23","resultStr":"{\"title\":\"The channeled-BSG: a universal floorplan for simultaneous place/route with IC applications\",\"authors\":\"S. Nakatake, K. Sakanushi, Y. Kajitani, M. Kawakita\",\"doi\":\"10.1145/288548.289064\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The BSG based packing of rectangles has been shown a breakthrough in problem size and generality, if routing is not involved. In order to include the routing, we define the channeled-BSG by associating the BSG-segs with channels. On the channeled-BSG, a new operation, flip, transforms an initial routing to another. Together with a formula that estimates the worst case width of channels for a given global routing, a solution space of simultaneous placement and routing is realized. It is proved that the space contains an optimal solution within the framework of the model. To search the space for a better solution, simulated annealing is implemented. Experiments to industrial data of analog LSIs showed a promising performance.\",\"PeriodicalId\":224802,\"journal\":{\"name\":\"1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)\",\"volume\":\"23 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1998-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"23\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1145/288548.289064\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/288548.289064","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The channeled-BSG: a universal floorplan for simultaneous place/route with IC applications
The BSG based packing of rectangles has been shown a breakthrough in problem size and generality, if routing is not involved. In order to include the routing, we define the channeled-BSG by associating the BSG-segs with channels. On the channeled-BSG, a new operation, flip, transforms an initial routing to another. Together with a formula that estimates the worst case width of channels for a given global routing, a solution space of simultaneous placement and routing is realized. It is proved that the space contains an optimal solution within the framework of the model. To search the space for a better solution, simulated annealing is implemented. Experiments to industrial data of analog LSIs showed a promising performance.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
