1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)最新文献

Polynomial methods for component matching and verification 多项式方法的组件匹配和验证

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) Pub Date : 1998-11-01 DOI: 10.1145/288548.289115

James Smith, G. Micheli

引用次数: 46

Slicing floorplans with pre-placed modules 使用预先放置的模块切片平面图

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) Pub Date : 1998-11-01 DOI: 10.1145/288548.288622

Evangeline F. Y. Young, D. F. Wong

引用次数: 44

Tight integration of combinational verification methods 组合验证方法的紧密集成

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) Pub Date : 1998-11-01 DOI: 10.1145/288548.289088

J. Burch, V. Singhal

引用次数: 73

On primitive fault test generation in non-scan sequential circuits 非扫描顺序电路中原始故障测试的产生

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) Pub Date : 1998-11-01 DOI: 10.1145/288548.288625

R. Tekumalla, P. R. Menon

引用次数: 2

A quantitative approach to development and validation of synthetic benchmarks for behavioral synthesis 开发和验证行为综合综合基准的定量方法

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) Pub Date : 1998-11-01 DOI: 10.1145/288548.289052

Chunho Lee, M. Potkonjak

引用次数: 2

On-line scheduling of hard real-time tasks on variable voltage processor 可变电压处理器上硬实时任务的在线调度

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) Pub Date : 1998-11-01 DOI: 10.1145/288548.289105

Inki Hong, M. Potkonjak, M. Srivastava

引用次数: 204

A new algorithm for the reduction of incompletely specified finite state machines 一种新的不完全指定有限状态机约简算法

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) Pub Date : 1998-11-01 DOI: 10.1145/288548.289075

J. M. Pena, Arlindo L. Oliveira

引用次数: 54

Simulation of high-Q oscillators 高q振荡器的仿真

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) Pub Date : 1998-11-01 DOI: 10.1145/288548.288601

M. Gourary, S. Ulyanov, M. Zharov, S. Rusakov

引用次数: 28

CORDS: hardware-software co-synthesis of reconfigurable real-time distributed embedded systems 可重构实时分布式嵌入式系统的软硬件协同合成

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) Pub Date : 1998-11-01 DOI: 10.1145/288548.288561

R. Dick, N. Jha

{"title":"CORDS: hardware-software co-synthesis of reconfigurable real-time distributed embedded systems","authors":"R. Dick, N. Jha","doi":"10.1145/288548.288561","DOIUrl":"https://doi.org/10.1145/288548.288561","url":null,"abstract":"Field programmable gate arrays (FPGAs) are commonly used in embedded systems. Although it is possible to reconfigure some FPGAs while an embedded system is operational, this feature is seldom exploited. Recent improvements in the flexibility and reconfiguration speed of FPGAs have made it practical to reconfigure them dynamically, reducing the amount of hardware required in an embedded system. We have developed a system, called CORDS, which synthesizes multi-rate, real-time, periodic distributed embedded systems containing dynamically reconfigurable FPGAs. Executing different tasks on the same FPGA requires that potentially time-consuming reconfiguration be carried out between tasks. CORDS uses a novel preemptive, dynamic priority, multi-rate scheduling algorithm to deal with this problem. To the best of our knowledge, dynamically reconfigured FPGAs have not previously been used in hardware-software co-synthesis of embedded systems. Experimental results indicate that using dynamically reconfigured FPGAs in distributed real-time embedded systems has the potential to reduce their price and allow the synthesis of architectures which meet system specifications that would otherwise be infeasible.","PeriodicalId":224802,"journal":{"name":"1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125468416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 99

A general approach for regularity extraction in datapath circuits 数据路径电路中规则性提取的一般方法

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) Pub Date : 1998-11-01 DOI: 10.1145/288548.289050

Amit Chowdhary, Sudhakar Kale, Phani K. Saripella, Naresh Sehgal, Rajesh K. Gupta

{"title":"A general approach for regularity extraction in datapath circuits","authors":"Amit Chowdhary, Sudhakar Kale, Phani K. Saripella, Naresh Sehgal, Rajesh K. Gupta","doi":"10.1145/288548.289050","DOIUrl":"https://doi.org/10.1145/288548.289050","url":null,"abstract":"In the majority of high performance custom IC designs, designers take advantage of the high degree of regularity present in circuits to generate efficient layouts in terms of area and performance as well as to reduce the design effort. We present a general and comprehensive approach to extract functional regularity for datapath circuits from their behavioral or structural HDL descriptions. The fundamental step is the generation of a large set of templates, where a template is a subcircuit with multiple instances in the circuit. Two novel template generation algorithms are presented-one for templates with a tree structure, and the other for a special class of multi output templates, called single principal output (single-PO) templates, where all outputs of a template are in the transitive fanin of a particular output. The set of templates generated is complete under a few simplifying, yet practical, assumptions. This is key to obtaining a desirable cover of the circuit using templates. We show that excellent covers are obtained for various circuits, including ISCAS benchmarks. We also demonstrate that the regularity extracted for these circuits can be used to understand their underlying structure. We have successfully used our approach to identify bit slices of very large datapath circuits from general purpose microprocessors.","PeriodicalId":224802,"journal":{"name":"1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125980514","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 44