1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)最新文献_第10页

Energy-efficiency in presence of deep submicron noise 在深亚微米噪声存在的能源效率

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) Pub Date : 1998-11-01 DOI: 10.1145/288548.288618

R. Hegde, Naresh R Shanbhag

{"title":"Energy-efficiency in presence of deep submicron noise","authors":"R. Hegde, Naresh R Shanbhag","doi":"10.1145/288548.288618","DOIUrl":"https://doi.org/10.1145/288548.288618","url":null,"abstract":"The article presents: 1) lower bounds on energy consumption of noisy digital gates and 2) the concept of noise tolerance via coding for achieving energy efficiency in the presence of noise. A discrete channel model for noisy digital logic in deep submicron technology that captures the manifestation of circuit noise is presented. The lower bounds are derived via an information-theoretic approach whereby a VLSI architecture implemented in a certain technology is viewed as a channel with information transfer capacity C (in bits/sec). A computing application is shown to require a minimum information transfer rate R (also in bits/sec). Lower bounds are obtained by employing the information theoretic constraint C>R. This constraint ensures reliability of computation though in an asymptotic sense. Lower bounds on transition activity at the output of noisy logic gates are also obtained using this constraint. Past work (for noiseless bus coding) is shown to fall out as a special case. In addition, lower bounds on energy dissipation is computed by solving an optimization problem where the objective function is the energy subject to the constraint of C>R. A surprising result is that in a scenario where capacitive component of power dissipation dominates: the voltage for minimum energy is greater than the minimum voltage for reliable operation. For an off-chip I/O signaling example, we show that the lower bounds are a factor of 24/spl times/ below present day systems and that a very simple Hamming code can reduce the energy consumption by a factor of 3/spl times/. This indicates the potential of noise tolerance in achieving low energy operation in the presence of noise.","PeriodicalId":224802,"journal":{"name":"1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114254930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 163

Efficient equivalence checking of multi-phase designs using retiming 采用重定时的多相设计的有效等效检验

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) Pub Date : 1998-11-01 DOI: 10.1145/288548.289086

Gagan Hasteer, Anmol Mathur, P. Banerjee

引用次数: 8

Lazy transition systems: application to timing optimization of asynchronous circuits 延迟转换系统:在异步电路时序优化中的应用

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) Pub Date : 1998-11-01 DOI: 10.1145/288548.288633

J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno, A. Taubin, A. Yakovlev

引用次数: 24

Optimal 2-D cell layout with integrated transistor folding 集成晶体管折叠的最佳二维单元布局

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) Pub Date : 1998-11-01 DOI: 10.1145/288548.288590

Avaneendra Gupta, J. Hayes

{"title":"Optimal 2-D cell layout with integrated transistor folding","authors":"Avaneendra Gupta, J. Hayes","doi":"10.1145/288548.288590","DOIUrl":"https://doi.org/10.1145/288548.288590","url":null,"abstract":"Folding, a key requirement in high performance cell layout, implies breaking a large transistor into smaller, equal sized transistors (legs) that are connected in parallel and placed contiguously with diffusion sharing. We present a novel technique, FCLIP, that integrates folding into the generation of optimal layouts of CMOS cells in the two dimensional (2D) style. FCLIP is based on integer linear programming (ILP) and precisely formulates cell width minimization as a 0-1 optimization problem. Folding is incorporated into the 0-1 ILP model by variables that represent the degrees of freedom that folding introduces into cell layout. FCLIP yields optimal results for three reasons: (1) it implicitly explores all possible transistor placements; (2) it considers all diffusion sharing possibilities among folded transistors; and (3) when paired P and N transistors have unequal numbers of legs, it considers all their relative positions. FCLIP is shown to be practical for relatively large circuits with up to 30 transistors, We then extend FCLIP to accommodate-and-stack clustering, a requirement in most practical designs due to its benefits to circuit performance. This reduces run times dramatically, making FCLIP viable for much larger circuits. It also demonstrates the versatility of FCLIP's ILP based approach in easily accommodating additional design constraints.","PeriodicalId":224802,"journal":{"name":"1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116637093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 26

Simulation of coupling capacitances using matrix partitioning 用矩阵分划法模拟耦合电容

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) Pub Date : 1998-11-01 DOI: 10.1145/288548.288554

Tuyen V. Nguyen, A. Devgan, A. Sadigh

引用次数: 6

Analysis of emerging core-based design lifecycle 新兴基于核心的设计生命周期分析

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) Pub Date : 1998-11-01 DOI: 10.1145/288548.289068

K. Kucukcakar

引用次数: 2

Noise considerations in circuit optimization 电路优化中的噪声考虑

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) Pub Date : 1998-11-01 DOI: 10.1145/288548.288617

C. Visweswariah, R. Haring, A. Conn

{"title":"Noise considerations in circuit optimization","authors":"C. Visweswariah, R. Haring, A. Conn","doi":"10.1145/288548.288617","DOIUrl":"https://doi.org/10.1145/288548.288617","url":null,"abstract":"Noise can cause digital circuits to switch incorrectly and thus produce spurious results. Noise can also have adverse power, timing and reliability effects. Dynamic logic is particularly susceptible to charge-sharing and coupling noise. Thus, the design and optimization of a circuit should take noise considerations into account. Such considerations are typically stated as semi-infinite constraints. In addition, the number of signals to be checked and the number of sub-intervals of time during which the checking must be performed can potentially be very large. Thus, the practical incorporation of noise constraints during circuit optimization is a hitherto unsolved problem. This paper describes a novel method for incorporating noise considerations during automatic circuit optimization. Semi-infinite constraints representing noise considerations are first converted to ordinary equality constraints involving time integrals, which are readily computed in the context of circuit optimization based on time-domain simulation. Next, the gradients of these integrals are computed by the adjoint method. By using an augmented Lagrangian optimization merit function, the adjoint method is applied to compute all the necessary gradients required for optimization in a single adjoint analysis, no matter how many noise measurements are considered, and irrespective of the dimensionality of the problem. Numerical results are presented.","PeriodicalId":224802,"journal":{"name":"1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125009094","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 51

Efficient analog circuit synthesis with simultaneous yield and robustness optimization 同时产率和鲁棒性优化的高效模拟电路合成

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) Pub Date : 1998-11-01 DOI: 10.1145/288548.288630

G. Debyser, G. Gielen

{"title":"Efficient analog circuit synthesis with simultaneous yield and robustness optimization","authors":"G. Debyser, G. Gielen","doi":"10.1145/288548.288630","DOIUrl":"https://doi.org/10.1145/288548.288630","url":null,"abstract":"The paper presents an efficient statistical design methodology that allows simultaneous sizing for performance and optimization for yield and robustness of analog circuits. The starting point of this methodology is a declarative analytical description of the circuit. An equation manipulation program based on constraint satisfaction converts this declarative model into an efficient design plan for optimization based sizing. The efficiency is due to the use of an operating point driven DC formulation, so that the design plan avoids the calculation of simultaneous sets of nonlinear equations. From the same declarative analytical description also a direct symbolic yield estimation plan is generated. The parametric yield is estimated by propagating the spread of the technological variables through the analytical model towards the performance variables of the circuit. The design plan and the yield estimation plan are then combined together in the inner loop of a global optimization routine. The strength of this methodology lies in the low CPU times needed to perform yield estimation compared to the hours of simulation batches with Monte Carlo simulations, while the accuracy is comparable.","PeriodicalId":224802,"journal":{"name":"1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126701876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 61

Arbitrary rectilinear block packing based on sequence pair 基于序列对的任意直线块填充

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) Pub Date : 1998-04-01 DOI: 10.1145/288548.288623

M. Kang, W. Dai

引用次数: 50

Integrating logic retiming and register placement 集成逻辑重定时和寄存器放置

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) Pub Date : 1900-01-01 DOI: 10.1109/iccad.1998.742863

Tzu Chieh Tien, Hsiao Pin Su, Yu Wen Tsay

引用次数: 0