Optimal 2-D cell layout with integrated transistor folding

Abstract

Folding, a key requirement in high performance cell layout, implies breaking a large transistor into smaller, equal sized transistors (legs) that are connected in parallel and placed contiguously with diffusion sharing. We present a novel technique, FCLIP, that integrates folding into the generation of optimal layouts of CMOS cells in the two dimensional (2D) style. FCLIP is based on integer linear programming (ILP) and precisely formulates cell width minimization as a 0-1 optimization problem. Folding is incorporated into the 0-1 ILP model by variables that represent the degrees of freedom that folding introduces into cell layout. FCLIP yields optimal results for three reasons: (1) it implicitly explores all possible transistor placements; (2) it considers all diffusion sharing possibilities among folded transistors; and (3) when paired P and N transistors have unequal numbers of legs, it considers all their relative positions. FCLIP is shown to be practical for relatively large circuits with up to 30 transistors, We then extend FCLIP to accommodate-and-stack clustering, a requirement in most practical designs due to its benefits to circuit performance. This reduces run times dramatically, making FCLIP viable for much larger circuits. It also demonstrates the versatility of FCLIP's ILP based approach in easily accommodating additional design constraints.