1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)最新文献

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Gate-size selection for standard cell libraries 标准细胞库的门大小选择
F. Beeftink, P. Kudva, David S. Kung, L. Stok
{"title":"Gate-size selection for standard cell libraries","authors":"F. Beeftink, P. Kudva, David S. Kung, L. Stok","doi":"10.1145/288548.289084","DOIUrl":"https://doi.org/10.1145/288548.289084","url":null,"abstract":"The paper presents an algorithm to select a good set of gate sizes for the primitive gates of a standard cell library. A measurement error on a gate is defined to quantify the discrepancy resulting from replacing the size required by a synthesis sizing algorithm with a size available in a discrete cell library. The criterion for gate size selection is a set of gate sizes that minimizes the cumulative error of a prescribed measurement. Optimal solutions to the gate size selection problem targetting size and delay measurements are presented for cases when the probability distribution and the delay equations are simple. A realistic probability distribution is obtained using a sample space of gates derived from a group of designs that is synthesized under the semi-custom synthesis methodology (K. Shepard et al., 1997). A \"delay match\" (minimizing delay error) and a \"size match\" (minimizing size error) set of gate sizes are obtained numerically and are subsequently realized as discrete cell libraries. The previous group of designs are synthesized using the two selected cell libraries and two other cell libraries, one with \"equal spacing\" of cell sizes and the other with \"exponential spacing\" of cell sizes. The \"size match\" library gives the best overall slack and area results.","PeriodicalId":224802,"journal":{"name":"1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132722027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 50
Technology mapping for domino logic domino逻辑的技术映射
Min Zhao, S. Sapatnekar
{"title":"Technology mapping for domino logic","authors":"Min Zhao, S. Sapatnekar","doi":"10.1145/288548.288621","DOIUrl":"https://doi.org/10.1145/288548.288621","url":null,"abstract":"Domino logic is a popular configuration for implementing high-speed circuits. An algorithm for domino logic mapping, under a parameterized library style, is presented. Practical design methods, such as the use of multi-output domino and wide domino gates, are incorporated within the technology mapping framework. The technique can handle large circuits with small computational overheads, and shows improvements of up to about 37% over existing methods.","PeriodicalId":224802,"journal":{"name":"1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125678441","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
Phase noise in oscillators: DAEs and colored noise sources 振荡器中的相位噪声:DAEs和彩色噪声源
A. Demir
{"title":"Phase noise in oscillators: DAEs and colored noise sources","authors":"A. Demir","doi":"10.1145/288548.288602","DOIUrl":"https://doi.org/10.1145/288548.288602","url":null,"abstract":"Oscillators are key components of electronic systems. Undesired perturbations, i.e. noise, in practical electronic systems adversely affect the spectral and timing properties of oscillators resulting in phase noise, which is a key performance limiting factor, being a major contributor to bit-error-rate (BER) of RF communication systems, and creating synchronization problems in clocked and sampled data systems. We first present a theory and numerical methods for nonlinear perturbation and noise analysis of oscillators described by a system of differential algebraic equations (DAEs), which extends our recent results on perturbation analysis of autonomous ordinary differential equations (ODEs). In developing the above theory, we rely on novel results we establish for linear periodically time varying (LPTV) systems: Floquet theory for DAEs. We then use this nonlinear perturbation analysis to derive the stochastic characterization, including the resulting oscillator spectrum, of phase noise in oscillators due to colored (e.g., 1/f noise), as opposed to white noise sources. The case of white noise sources has already been treated by us in a recent publication (A. Demir et al., 1998). The results of the theory developed in this work enabled us to implement a rigorous and effective analysis and design tool in a circuit simulator for low phase noise oscillator design.","PeriodicalId":224802,"journal":{"name":"1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133077551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 100
Symbolic algorithms for layout-oriented synthesis of pass transistor logic circuits 面向布局的通型晶体管逻辑电路合成的符号算法
Fabrizio Ferrandi, A. Macii, E. Macii, M. Poncino, R. Scarsi, F. Somenzi
{"title":"Symbolic algorithms for layout-oriented synthesis of pass transistor logic circuits","authors":"Fabrizio Ferrandi, A. Macii, E. Macii, M. Poncino, R. Scarsi, F. Somenzi","doi":"10.1145/288548.288619","DOIUrl":"https://doi.org/10.1145/288548.288619","url":null,"abstract":"The paper presents a novel methodology for synthesizing PTL circuits, whose distinctive features are the use of a symbolic algorithm for the covering of the initial network in terms of PTL cells, and the exploitation of layout level area and delay model during the selection of the best covering solution. The results produced by the synthesis procedure on the full suite of the Iscas'85 combinational circuits are very encouraging.","PeriodicalId":224802,"journal":{"name":"1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)","volume":"121 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131527512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
Integrating floorplanning in data-transfer based high-level synthesis 在基于数据传输的高级综合中集成楼层规划
Shantanu Tarafdar, M. Leeser, Zixin Yin
{"title":"Integrating floorplanning in data-transfer based high-level synthesis","authors":"Shantanu Tarafdar, M. Leeser, Zixin Yin","doi":"10.1145/288548.289063","DOIUrl":"https://doi.org/10.1145/288548.289063","url":null,"abstract":"Modern digital systems move and process vast amounts of data. Designing good ASIC architectures for these systems requires efficient data routing and storage. A high level synthesis (HLS) system must consider spatial aspects of the architecture it synthesizes to achieve this. We discuss using floorplanning information in the main HLS flow. Our HLS system, Midas, incorporates floorplanning and formulates HLS using a data transfer model. Midas synthesizes an architecture whose data storage and transfer subsystems are spatially integrated with its execution unit. Midas also generates a high level floorplan for the architecture, which contains the shapes and coordinates of its components and routing channel specifications for its buses. Our experiments comparing Midas's architectures to those generated by a HLS system that does not use the data transfer model or floorplanning show that Midas's architectures are smaller and yet allow for large amounts of simultaneous data motion and storage.","PeriodicalId":224802,"journal":{"name":"1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123714222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
Testability analysis and multi-frequency ATPG for analog circuits and systems 模拟电路和系统的可测试性分析和多频ATPG
S. Huynh, Seongwon Kim, M. Soma, Jinyan Zhang
{"title":"Testability analysis and multi-frequency ATPG for analog circuits and systems","authors":"S. Huynh, Seongwon Kim, M. Soma, Jinyan Zhang","doi":"10.1145/288548.289057","DOIUrl":"https://doi.org/10.1145/288548.289057","url":null,"abstract":"Fast and efficient test generation techniques are key to reducing the current high cost of testing analog circuits. A new multi-frequency test generation technique for detecting catastrophic failures in this class of circuits is presented. Testability transfer factors are introduced and we use them to construct an efficient test set for analog circuits. Fault detectability and fault coverage are also defined. Two circuits from the suite of analog and mixed-signal benchmark circuits are used to validate our approach.","PeriodicalId":224802,"journal":{"name":"1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125323156","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Period assignment in multidimensional periodic scheduling 多维周期调度中的周期分配
W. Verhaegh, E. Aarts, Paul C. N. van Gorp
{"title":"Period assignment in multidimensional periodic scheduling","authors":"W. Verhaegh, E. Aarts, Paul C. N. van Gorp","doi":"10.1145/288548.289090","DOIUrl":"https://doi.org/10.1145/288548.289090","url":null,"abstract":"We discuss the problem of assigning periods in multidimensional periodic scheduling such that storage costs are minimized. This problem originates from the design of high throughput DSP systems, where highly parallel execution of loops is of utmost importance, and thus finding an optimal order of the loops is an important task. We formulate the period assignment problem as a linear programming (LP) problem with some additional, nonlinear constraints. The nonlinear constraints are handled by a branch and bound approach, whereas the LP relaxation is handled by a constraint generation technique. The effectiveness and efficiency of the approach are good, which is illustrated by means of some practical examples.","PeriodicalId":224802,"journal":{"name":"1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127295981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Functional debugging of systems-on-chip 片上系统的功能调试
D. Kirovski, M. Potkonjak, L. Guerra
{"title":"Functional debugging of systems-on-chip","authors":"D. Kirovski, M. Potkonjak, L. Guerra","doi":"10.1145/288548.289081","DOIUrl":"https://doi.org/10.1145/288548.289081","url":null,"abstract":"Due to the exponential growth of both design complexity and the number of gates per pin, functional debugging has emerged as a critical step in the development of a system-on-chip. We introduce a novel debugging approach for programmable systems-on-chip. The new method leverages the advantages of the two complementary functional execution approaches, emulation and simulation. We have developed a set of tools, transparent to both the design and debugging process, which enables the user to run long test sequences in emulation, and upon error detection, roll-back to an arbitrary instance in execution time, and switch over to simulation based debugging for full design visibility and controllability. The efficacy of the approach is dependent on the method for transferring the computation from one execution domain to another. To enable effective transfer of the computation state, we have identified a set of optimization tasks, established their computation complexity, and developed an efficient suite of optimization algorithms.","PeriodicalId":224802,"journal":{"name":"1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121994877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
SpC: synthesis of pointers in C application of pointer analysis to the behavioral synthesis from C 指针的综合C中的应用指针分析从行为综合C
L. Semeria, G. Micheli
{"title":"SpC: synthesis of pointers in C application of pointer analysis to the behavioral synthesis from C","authors":"L. Semeria, G. Micheli","doi":"10.1145/288548.289051","DOIUrl":"https://doi.org/10.1145/288548.289051","url":null,"abstract":"As designers may model mixed software-hardware systems using a subset of C or C++, we present SpC, a solution to synthesize and optimize a C model with pointers. In hardware, a pointer is not only the address of data in memory, but it may also reference multiple variables mapped to registers, ports or wires. Pointer analysis is used to find the point-to-set of each pointer in the program. We address the problem of synthesizing and optimizing pointers to multiple variables and array elements. Temporary variables are defined to optimize loads and stores by minimizing the number of live variables. The combinational logic can also be reduced by encoding the pointer values. An implementation using the SUIF framework is presented, followed by some case studies such as the synthesis of a 2D IDCT.","PeriodicalId":224802,"journal":{"name":"1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127562934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 88
Model reduction of time-varying linear systems using approximate multipoint Krylov-subspace projectors 使用近似多点krylov -子空间投影的时变线性系统模型简化
J. Phillips
{"title":"Model reduction of time-varying linear systems using approximate multipoint Krylov-subspace projectors","authors":"J. Phillips","doi":"10.1145/288548.288583","DOIUrl":"https://doi.org/10.1145/288548.288583","url":null,"abstract":"A method is presented for model reduction of systems described by time varying differential algebraic equations. This method allows automated extraction of reduced models for nonlinear RF blocks, such as mixers and filters, that have a near linear signal path but may contain strongly nonlinear time varying components. The models have the accuracy of a transistor level nonlinear simulation, but are very compact and so can be used in system level simulation and design. The model reduction procedure is based on a multipoint rational approximation algorithm formed by orthogonal projection of the original time varying linear system into an approximate Krylov subspace. The models obtained from the approximate Krylov subspace projector can be obtained much more easily than the exact projectors but show negligible difference in accuracy.","PeriodicalId":224802,"journal":{"name":"1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130560790","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 69
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