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1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)最新文献

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A fast, accurate, and non-statistical method for fault coverage estimation 一种快速、准确、非统计的故障覆盖估计方法
1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) Pub Date : 1998-11-01 DOI: 10.1145/288548.288594
M. Hsiao
{"title":"A fast, accurate, and non-statistical method for fault coverage estimation","authors":"M. Hsiao","doi":"10.1145/288548.288594","DOIUrl":"https://doi.org/10.1145/288548.288594","url":null,"abstract":"We present a fast, dynamic fault coverage estimation technique for sequential circuits that achieves high degrees of accuracy by significantly reducing the number of injected faults and faulty-event evaluations. Specifically, we dynamically reduce injection of two types of faults: (1) hyperactive faults that never get detected, and (2) faults whose effects never propagate to a flip-flop or primary output. The cost of fault simulation is greatly reduced as injection of most of these two types of faults is prevented. Experiments show that our technique gives very accurate estimates with frequently greater speedups than the sampling techniques for most circuits. Most significantly, the proposed technique can be combined with the sampling approach to obtain speedups equivalent of small sample sizes and retain estimation accuracy of large fault samples.","PeriodicalId":224802,"journal":{"name":"1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125726883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
On the optimization power of retiming and resynthesis transformations 论重定时和再合成变换的优化能力
1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) Pub Date : 1998-11-01 DOI: 10.1145/288548.289061
R. Ranjan, V. Singhal, F. Somenzi, R. Brayton
{"title":"On the optimization power of retiming and resynthesis transformations","authors":"R. Ranjan, V. Singhal, F. Somenzi, R. Brayton","doi":"10.1145/288548.289061","DOIUrl":"https://doi.org/10.1145/288548.289061","url":null,"abstract":"Retiming and resynthesis transformations can be used for optimizing the area, power, and delay of sequential circuits. Even though this technique has been known for more than a decade, its exact optimization capability has not been formally established. We show that retiming and resynthesis can exactly implement 1-step equivalent state transition graph transformations. This result is the strongest to date. We also show how the notions of retiming and resynthesis can be moderately extended to achieve more powerful state transition graph transformations. Our work will provide theoretical foundation for practical retiming and resynthesis based optimization and verification.","PeriodicalId":224802,"journal":{"name":"1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)","volume":"EMC-18 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132898976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
Implementation and use of SPFDs in optimizing Boolean networks 在布尔网络优化中spfd的实现和使用
1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) Pub Date : 1998-11-01 DOI: 10.1145/288548.288584
Subarnarekha Sinha, R. Brayton
{"title":"Implementation and use of SPFDs in optimizing Boolean networks","authors":"Subarnarekha Sinha, R. Brayton","doi":"10.1145/288548.288584","DOIUrl":"https://doi.org/10.1145/288548.288584","url":null,"abstract":"S. Yamashita et al. (1996) introduced a new category for expressing the flexibility that a node can have in a multi level network. Originally presented in the context of FPGA synthesis, the paper has wider implications which were discussed by R.K. Brayton (1997). SPFDs are essentially a set of incompletely specified functions. The increased flexibility that they offer is obtained by allowing both a node to change as well as its immediate fanins. The challenge with SPFDs is: (1) to compute them in an efficient way, and (2) to use their increased flexibility in a controlled way to optimize a circuit. We provide a complete implementation of SPFDs using BDDs and apply it to the optimization of Boolean networks. Two scenarios are presented, one which trades literals for wires and the other rewires the network by replacing one fanin at a node by a new fanin. Results on benchmark circuits are very favorable.","PeriodicalId":224802,"journal":{"name":"1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127168646","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 61
Sampling schemes for computing OBDD variable orderings 计算OBDD变量排序的抽样方案
1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) Pub Date : 1998-11-01 DOI: 10.1145/288548.289099
J. Jain, William Adams, M. Fujita
{"title":"Sampling schemes for computing OBDD variable orderings","authors":"J. Jain, William Adams, M. Fujita","doi":"10.1145/288548.289099","DOIUrl":"https://doi.org/10.1145/288548.289099","url":null,"abstract":"We suggest some novel variable ordering techniques based upon the notion of sampling. Such techniques can produce highly effective static variable orders, and can thus be employed in numerous problems where current static variable ordering techniques prove totally inadequate. They can also augment various reordering techniques thereby helping to produce far superior variable orders in a comparable, or lesser, amount of time. Importantly, we have been able to build BDDs of circuits which could not be represented previously using numerous other reordering packages.","PeriodicalId":224802,"journal":{"name":"1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126987452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 34
Representation of process mode correlation for scheduling 用于调度的进程模式关联的表示
1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) Pub Date : 1998-11-01 DOI: 10.1145/288548.288560
D. Ziegenbein, K. Richter, R. Ernst, J. Teich, L. Thiele
{"title":"Representation of process mode correlation for scheduling","authors":"D. Ziegenbein, K. Richter, R. Ernst, J. Teich, L. Thiele","doi":"10.1145/288548.288560","DOIUrl":"https://doi.org/10.1145/288548.288560","url":null,"abstract":"The specification of embedded systems very often contains a mixture of different models of computation. In particular the data flow and control flow associated to the transformative and reactive domains, respectively are tightly coupled. The paper considers classes of applications that feature communicating processes whose functions depend on a finite set of computation modes. The change between these modes is synchronized by data communication. An approach is presented to model the correlation of process modes and to fully utilize this information for scheduling. A modeling example shows the optimization potential of the new approach.","PeriodicalId":224802,"journal":{"name":"1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)","volume":"1 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116780751","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 32
Verification by approximate forward and backward reachability 通过近似前向和后向可达性进行验证
1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) Pub Date : 1998-11-01 DOI: 10.1145/288548.289055
S. Govindaraju, D. Dill
{"title":"Verification by approximate forward and backward reachability","authors":"S. Govindaraju, D. Dill","doi":"10.1145/288548.289055","DOIUrl":"https://doi.org/10.1145/288548.289055","url":null,"abstract":"Approximate reachability techniques trade off accuracy for the capacity to deal with bigger designs. In this paper, we extend the idea of approximations using overlapping projections to symbolic backward reachability. This is combined with a previous method of computing overapproximate forward reachable state sets using overlapping projections. The algorithm computes a superset of the set of states that lie on a path from the initial state to a state that violates a specified invariant property. If this set is empty, there is no possibility of violating the invariant. If this set is non-empty, it may be possible to prove the existence of such a path by searching for a counter-example. A simple heuristic is given, which seems to work well in practice, for generating a counter-example path from this approximation. We evaluate these new algorithms by applying them to several control modules from the I/O unit in the Stanford FLASH Multiprocessor.","PeriodicalId":224802,"journal":{"name":"1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114609191","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 38
Determination of worst-case aggressor alignment for delay calculation 延迟计算中最坏情况攻击者对准的确定
1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) Pub Date : 1998-11-01 DOI: 10.1145/288548.288616
Paul D. Gross, Ravishankar Arunachalam, K. Rajagopal, L. Pileggi
{"title":"Determination of worst-case aggressor alignment for delay calculation","authors":"Paul D. Gross, Ravishankar Arunachalam, K. Rajagopal, L. Pileggi","doi":"10.1145/288548.288616","DOIUrl":"https://doi.org/10.1145/288548.288616","url":null,"abstract":"Increases in delay due to coupling can have a dramatic impact on IC performance for deep submicron technologies. To achieve maximum performance there is a need for analyzing logic stages with large complex coupled interconnects. In timing analysis, the worst case delay of gates along a critical path must include the effect of noise due to switching of nearby aggressor gates. We propose a new waveform iteration strategy to compute the delay in the presence of coupling and to align aggressor inputs to determine the worst case victim delay. We demonstrate the application of our methodology at both the transistor level and cell level. In addition, we prove that the waveforms generated in our methodology converge under typical timing analysis conditions.","PeriodicalId":224802,"journal":{"name":"1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114780769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 125
The multi-BSG: stochastic approach to an optimum packing of convex-rectilinear blocks 凸直线块的最佳填充的多重bsg:随机方法
1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) Pub Date : 1998-11-01 DOI: 10.1145/288548.288624
K. Sakanushi, S. Nakatake, Y. Kajitani
{"title":"The multi-BSG: stochastic approach to an optimum packing of convex-rectilinear blocks","authors":"K. Sakanushi, S. Nakatake, Y. Kajitani","doi":"10.1145/288548.288624","DOIUrl":"https://doi.org/10.1145/288548.288624","url":null,"abstract":"A floorplanner that can handle convex-rectilinear blocks is developed by enhancing the BSG-based packing algorithm. The ideas are in the introduction of (1) multi-rectangle representation of a block as a superpose of element-rectangles, (2) parametric-BSG as a generalization of the BSG, (3) multi-BSG which is an arrangement of plural BSG's on a multi-layer, and (4) layer sharing condition of element-rectangles so that non-overlapping is discussed on each layer. A solution space of packings is defined as the set of packings generated by changing parametric-BSG and room assignments. It is guaranteed to contain an optimal packing if the BSG is not smaller than a certain size. A floorplan based on a simulated annealing was implemented. In experiments, it output highly compressed packings.","PeriodicalId":224802,"journal":{"name":"1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)","volume":"306 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123094208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
Wireplanning in logic synthesis 逻辑合成中的线规划
1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) Pub Date : 1998-11-01 DOI: 10.1145/288548.288556
W. Gosti, A. Narayan, R. Brayton, A. Sangiovanni-Vincentelli
{"title":"Wireplanning in logic synthesis","authors":"W. Gosti, A. Narayan, R. Brayton, A. Sangiovanni-Vincentelli","doi":"10.1145/288548.288556","DOIUrl":"https://doi.org/10.1145/288548.288556","url":null,"abstract":"In this paper, we propose a new logic synthesis methodology to deal with the increasing importance of the interconnect delay in deep submicron technologies. We first show that conventional logic synthesis techniques can produce circuits which will have long paths even if placed optimally. Then, we characterize the conditions under which this can happen and propose logic synthesis techniques which produce circuits which are \"better\" for placement. Our proposed approach still separates logic synthesis from physical design.","PeriodicalId":224802,"journal":{"name":"1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116898931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 49
Signature hiding techniques for FPGA intellectual property protection FPGA知识产权保护的签名隐藏技术
1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) Pub Date : 1998-11-01 DOI: 10.1145/288548.288606
J. Lach, W. Mangione-Smith, M. Potkonjak
{"title":"Signature hiding techniques for FPGA intellectual property protection","authors":"J. Lach, W. Mangione-Smith, M. Potkonjak","doi":"10.1145/288548.288606","DOIUrl":"https://doi.org/10.1145/288548.288606","url":null,"abstract":"This work presents the first known attempt to leverage the unique characteristics of FPGAs to protect commercial investments in intellectual property. A watermark is applied to the physical layout of a digital circuit when it is mapped into an FPGA. This watermark uniquely identifies the circuit origin and yet is difficult to detect. While this approach imposes additional constraints, experiments involving a number of large complex designs indicate that the performance impact is small.","PeriodicalId":224802,"journal":{"name":"1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132574310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 90
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