Symbolic algorithms for layout-oriented synthesis of pass transistor logic circuits

Abstract

The paper presents a novel methodology for synthesizing PTL circuits, whose distinctive features are the use of a symbolic algorithm for the covering of the initial network in terms of PTL cells, and the exploitation of layout level area and delay model during the selection of the best covering solution. The results produced by the synthesis procedure on the full suite of the Iscas'85 combinational circuits are very encouraging.