1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)最新文献

筛选
英文 中文
On accelerating pattern matching for technology mapping 加速技术映射模式匹配的研究
Y. Matsunaga
{"title":"On accelerating pattern matching for technology mapping","authors":"Y. Matsunaga","doi":"10.1145/288548.288587","DOIUrl":"https://doi.org/10.1145/288548.288587","url":null,"abstract":"The pattern matching algorithm is simple and fast compared to other such matching algorithms such as Boolean matching. One major drawback of the pattern matching is that there is a case where a cell needs a lot of patterns representing its logic function. That is because patterns are decomposed into 2-AND/NOT patterns to match against decomposed subject graphs. Furthermore, the conventional technology mapper does not pay much attention to relations among patterns. Each pattern is tried to match independently. A novel pattern matching algorithm that does not require patterns to be decomposed and couple speeding up techniques utilizing inter-relations among cells are described. These methods are very effective for large cell libraries with complex cells. Experimental results show that our methods gain matching time up to 40 times faster.","PeriodicalId":224802,"journal":{"name":"1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132013165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Formal verification of pipeline control using controlled token nets and abstract interpretation 使用受控令牌网和抽象解释的管道控制的形式化验证
Pei-Hsin Ho, Adrian J. Isles, T. Kam
{"title":"Formal verification of pipeline control using controlled token nets and abstract interpretation","authors":"Pei-Hsin Ho, Adrian J. Isles, T. Kam","doi":"10.1145/288548.289082","DOIUrl":"https://doi.org/10.1145/288548.289082","url":null,"abstract":"We present an automated formal verification method that can detect common pipeline control bugs of logic design components containing thousands of registers. The method models logic designs using controlled token nets. A controlled token net consists of: a token net that models the data flow in the datapath using token semantics; a control logic that models the control machines using traditional finite state semantics. We provide algorithms to: (1) extract a controlled token net from a logic design; (2) minimize the controlled token net; and (3) compute an abstract interpretation of the controlled token net for efficient model checking. We implemented and applied the method to 6 Intel logic design components containing up to 4500 registers and successfully detected 8 pre-silicon errata.","PeriodicalId":224802,"journal":{"name":"1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)","volume":"113 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132116416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 44
The design of a cache-friendly BDD library 缓存友好型BDD库的设计
D. E. Long
{"title":"The design of a cache-friendly BDD library","authors":"D. E. Long","doi":"10.1145/288548.289102","DOIUrl":"https://doi.org/10.1145/288548.289102","url":null,"abstract":"We describe the architecture for a new BDD library that is designed to be cache-friendly. The library incorporates a novel technique for terminating searches early during find operations together with a regrouping garbage collector. These features lead to a factor of two improvement in speed on typical examples compared to existing libraries.","PeriodicalId":224802,"journal":{"name":"1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134277189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
Power invariant vector sequence compaction 幂不变向量序列压缩
Ali Pinar, C. Liu
{"title":"Power invariant vector sequence compaction","authors":"Ali Pinar, C. Liu","doi":"10.1145/288548.289073","DOIUrl":"https://doi.org/10.1145/288548.289073","url":null,"abstract":"Simulation-based power estimation is commonly used for its high accuracy, despite excessive computation times. Techniques have been proposed to speed it up by transforming a given sequence into a shorter one while preserving the power consumption characteristics of the original sequence. This work proposes a novel method to compact a given input vector sequence to improve on the existing techniques. We propose a graph model to transform the problem to the problem of finding a heaviest weighted trail in a directed graph. We also propose a heuristic based on min-cost flow algorithms, using the graph model. Furthermore, we show that generating multiple input sequences yields better solutions in terms of both accuracy and simulation time. Experiments showed that significant reduction in simulation times can be achieved with extremely accurate results. Experiments also showed that the generation of multiple sequences improved the results further both in terms of accuracy and simulation time.","PeriodicalId":224802,"journal":{"name":"1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)","volume":"252 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131486611","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Test set compaction algorithms for combinational circuits 组合电路的测试集压缩算法
Ilker Hamzaoglu, J. Patel
{"title":"Test set compaction algorithms for combinational circuits","authors":"Ilker Hamzaoglu, J. Patel","doi":"10.1145/288548.288615","DOIUrl":"https://doi.org/10.1145/288548.288615","url":null,"abstract":"This paper presents two new algorithms, Redundant Vector Elimination (RVE) and Essential Fault Reduction (EFR), for generating compact test sets for combinational circuits under the single stuck at fault model, and a new heuristic for estimating the minimum single stuck at fault test set size. These algorithms together with the dynamic compaction algorithm are incorporated into an advanced ATPG system for combinational circuits, called MinTest. MinTest found better lower bounds and generated smaller test sets than the previously published results for the ISCAS85 and full scan version of the ISCAS89 benchmark circuits.","PeriodicalId":224802,"journal":{"name":"1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133728009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 479
High-level variable selection for partial-scan implementation 部分扫描实现的高级变量选择
Frank F. Hsu, J. Patel
{"title":"High-level variable selection for partial-scan implementation","authors":"Frank F. Hsu, J. Patel","doi":"10.1145/288548.288564","DOIUrl":"https://doi.org/10.1145/288548.288564","url":null,"abstract":"We propose a high level variable selection for partial scan approach to improve the testability of digital systems. The testability of a design is evaluated at the high level based on previously proposed controllability and observability measures. A testability grading technique is utilized to measure the relative testability improvement in a design, as the result of making a subset of the variables fully controllable and observable. The variables that cause the greatest testability improvement are selected and the selection process is performed incrementally until no further testability improvement can be achieved. Then the registers that correspond to the selected variables are placed in the scan chain for partial scan implementation. The experimental results show that the variable selection approach produces partial scan implementations that can achieve high fault coverage, while the logic overheads are fairly low.","PeriodicalId":224802,"journal":{"name":"1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126046058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Static power optimization of deep submicron CMOS circuits for dual V/sub T/ technology 双V/sub / T/技术下深亚微米CMOS电路的静态功率优化
Qi Wang, S. Vrudhula
{"title":"Static power optimization of deep submicron CMOS circuits for dual V/sub T/ technology","authors":"Qi Wang, S. Vrudhula","doi":"10.1145/288548.289076","DOIUrl":"https://doi.org/10.1145/288548.289076","url":null,"abstract":"We address the problem of delay constrained minimization of leakage power of CMOS digital circuits for dual V/sub T/ technology. A novel and efficient heuristic alogrithm based on circuit graph enumeration is proposed. The experimental results on the MCNC91 benchmark circuits show that up to an order of magnitude power reduction can be achieved without any increase in delay.","PeriodicalId":224802,"journal":{"name":"1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124887459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 109
Using precomputation in architecture and logic resynthesis 预计算在体系结构和逻辑合成中的应用
S. Hassoun, C. Ebeling
{"title":"Using precomputation in architecture and logic resynthesis","authors":"S. Hassoun, C. Ebeling","doi":"10.1145/288548.288632","DOIUrl":"https://doi.org/10.1145/288548.288632","url":null,"abstract":"Although tremendous advances have been accomplished in logic synthesis in the past two decades, in some cases logic synthesis still cannot attain the improvements possible by clever designers. This, in part, is a result of logic synthesis not optimizing across register boundaries. We focus on precomputation as a resynthesis technique capable of resynthesizing across register boundaries. By using precomputation, a critical signal is computed earlier in time, thus allowing it to be combinationally optimized with logic from previous pipeline stages. Precomputation automatically discovers some standard circuit transformations like bypassing and lookahead. In addition, precomputation can be used in conjunction with combinational logic synthesis to resynthesize a circuit to obtain better performance. The paper contributes to the understanding and development of precomputation. First, it provides a synthesis algorithm for precomputation. Second, it demonstrates how precomputation can be used to improve sequential logic resynthesis and reports the results of applying a heuristic to a subset of the MCNC benchmarks. Third, it illustrates how precomputation generalizes and unifies bypassing and lookahead-two important and practical architectural transformations often used in processor design and high level synthesis of DSP processors. Finally, it clarifies the relationships among precomputation, retiming, and implicit retiming.","PeriodicalId":224802,"journal":{"name":"1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125025869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Techniques for energy minimization of communication pipelines 通信管道能量最小化技术
Gang Qu, M. Potkonjak
{"title":"Techniques for energy minimization of communication pipelines","authors":"Gang Qu, M. Potkonjak","doi":"10.1145/288548.289092","DOIUrl":"https://doi.org/10.1145/288548.289092","url":null,"abstract":"The performance of many modern computer and communication systems is dictated by latency of communication pipelines. At the same time, power consumption is often another limiting factor in many portable systems. We address the problem of how to minimize the power consumption in system level pipelines under latency constraints. In particular, we exploit advantages provided by variable voltage design methodology to optimally select speed and therefore voltage of each pipeline stage. We define the problem and solve it optimally under realistic and widely accepted assumptions. We apply the obtained theoretical results to develop algorithms for power minimization of computer and communication systems and show that significant power reduction is possible without additional latency.","PeriodicalId":224802,"journal":{"name":"1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127040531","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Graph matching-based algorithms for FPGA segmentation design 基于图匹配算法的FPGA分段设计
Yao-Wen Chang, Jai-Ming Lin, D. F. Wong
{"title":"Graph matching-based algorithms for FPGA segmentation design","authors":"Yao-Wen Chang, Jai-Ming Lin, D. F. Wong","doi":"10.1145/288548.288557","DOIUrl":"https://doi.org/10.1145/288548.288557","url":null,"abstract":"Process technology advances will soon make the one-million gate FPGA a reality. A key issue that needs to be solved for the large-scale FPGAs to realize their full potential lies in the design of their segmentation architectures. One-dimensional segmentation designs have been studied to some degree in much of the literature; most of the previously proposed methods are based on stochastic or analytical analysis. In this paper, we address a new direction for studying segmentation architectures. Our method is based on graph-theoretic formulation. We first formulate a net matching problem and present a polynomial-time optimal algorithm to solve the problem. Based on the solution to the problem, we develop an effective and efficient matching-based algorithm for FPGA segmentation designs. Experimental results show that our method significantly outperforms previous work.","PeriodicalId":224802,"journal":{"name":"1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126629126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信