Static power optimization of deep submicron CMOS circuits for dual V/sub T/ technology

Abstract

We address the problem of delay constrained minimization of leakage power of CMOS digital circuits for dual V/sub T/ technology. A novel and efficient heuristic alogrithm based on circuit graph enumeration is proposed. The experimental results on the MCNC91 benchmark circuits show that up to an order of magnitude power reduction can be achieved without any increase in delay.