1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)最新文献_第3页

Communication synthesis for distributed embedded systems 分布式嵌入式系统的通信综合

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) Pub Date : 1998-11-01 DOI: 10.1145/288548.289067

R. Ortega, G. Borriello

引用次数: 73

Domino logic synthesis using complex static gates 使用复杂静态门的Domino逻辑合成

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) Pub Date : 1998-11-01 DOI: 10.1145/288548.288620

T. Thorp, G. Yee, C. Sechen

{"title":"Domino logic synthesis using complex static gates","authors":"T. Thorp, G. Yee, C. Sechen","doi":"10.1145/288548.288620","DOIUrl":"https://doi.org/10.1145/288548.288620","url":null,"abstract":"We address the synthesis of the most general form of a domino gate (dynamic-static domino), which consists of the pairing of a dynamic gate with any inverting static gate. All previous work focused on the synthesis of the most basic domino gate (standard domino), where the inverting static gate is an inverter. We developed a methodology and tools for synthesizing random logic blocks using both dynamic and complex inverting static gates in an alternating fashion. Dynamic-static (DS) domino can be used to reduce both gate levels and clock loading compared to standard domino. Comparisons between DS domino, standard domino, and static CMOS logic families are provided for six MCNC combinational logic benchmark circuits. Spice simulations show DS domino to have an average speed improvement of 53% over static CMOS and an average speed improvement of 17% over standard domino. DS domino also reduced clock loading by an average of 48% over standard domino. The paper introduces DS domino and presents a methodology for synthesizing random logic circuits using DS domino and other monotonic logic families such as Zipper CMOS.","PeriodicalId":224802,"journal":{"name":"1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)","volume":"120 7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126306383","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 29

Fanout optimization under a submicron transistor-level delay model 亚微米晶体管级延迟模型下扇出优化

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) Pub Date : 1998-11-01 DOI: 10.1145/288548.289085

P. Cocchini, Massoud Pedram, G. Piccinini, M. Zamboni

{"title":"Fanout optimization under a submicron transistor-level delay model","authors":"P. Cocchini, Massoud Pedram, G. Piccinini, M. Zamboni","doi":"10.1145/288548.289085","DOIUrl":"https://doi.org/10.1145/288548.289085","url":null,"abstract":"We present a new fanout optimization algorithm which is particularly suitable for digital circuits designed with submicron CMOS technologies. Restricting the class of fanout trees to the so-called bipolar LT-trees, the topology of the optimal fanout tree is found by means of a dynamic programming algorithm. The buffer selection is in turn performed by using a continuous buffer sizing technique based on a very accurate delay model especially developed for submicron CMOS processes. The fanout trees can distribute a signal with arbitrary polarity from the root of the tree to a set of sinks with arbitrary required time, required minimum signal slope, polarity and capacitive load. These trees can be constructed to maximize the required time at the root or to minimize the total buffer area under a required time constraint at the root. The performance of the algorithm shows several improvements with respect to conventional fanout optimization methods. More precisely, the area and delay improvements are 28% and 7%, respectively, when the algorithm is applied to entire circuits.","PeriodicalId":224802,"journal":{"name":"1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115961399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

PowerDrive: a fast, canonical POWER estimator for DRIVing synthEsis PowerDrive:用于驱动合成的快速，规范的功率估计器

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) Pub Date : 1998-11-01 DOI: 10.1145/288548.289094

S. Roy, H. Arts, P. Banerjee

引用次数: 2

Architecture driven circuit partitioning 架构驱动电路划分

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) Pub Date : 1998-11-01 DOI: 10.1145/288548.289062

Chau-Shen Chen, TingTing Hwang, C. L. Liu

引用次数: 8

Asymptotically efficient retiming under setup and hold constraints 在设置和保持约束下的渐近有效重定时

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) Pub Date : 1998-11-01 DOI: 10.1145/288548.289060

M. Papaefthymiou

引用次数: 20

Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation 用拉格朗日松弛法快速精确地同时确定门和线的尺寸

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) Pub Date : 1998-11-01 DOI: 10.1145/288548.289097

C. C. Chen, C. Chu, Martin D. F. Wong

引用次数: 270

Full-chip verification of UDSM designs UDSM设计的全芯片验证

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) Pub Date : 1998-11-01 DOI: 10.1145/288548.289070

R. Saleh, D. Overhauser, S. Taylor

引用次数: 30

Delay-oriented technology mapping for heterogeneous FPGAs with bounded resources 具有有限资源的异构fpga面向延迟的技术映射

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) Pub Date : 1998-11-01 DOI: 10.1145/288548.288558

J. Cong, Songjie Xu

{"title":"Delay-oriented technology mapping for heterogeneous FPGAs with bounded resources","authors":"J. Cong, Songjie Xu","doi":"10.1145/288548.288558","DOIUrl":"https://doi.org/10.1145/288548.288558","url":null,"abstract":"In order to maximize performance and device utilization, recent generation of FPGAs take advantage of speed and density benefits resulted from heterogeneous FPGAs, which provide either an array of homogeneous programmable logic blocks (PLBs), each configured to implement circuits with LUTs of different sizes, or an array of physically heterogeneous LUTs. Some heterogeneous FPGAs do not have limitations on the availability of LUTs of specific sizes within chip capacity due to the configuration flexibility of their PLBs, while others, such as Altera FLEX10K devices and Vantis VF1 FPGAs, have limited number of LUTs of certain types (such as embedded memory blocks), which we call heterogeneous FPGAs with bounded resources. LUTs of different sizes usually have different delays. In this paper, we study the technology mapping problem for delay minimization for heterogeneous FPGAs with bounded resources. We show that it is NP-Hard for general networks, but can be solved optimally in pseudo-polynomial time for trees. We then present two heuristic algorithms, named BinaryHM and CN-HM, for delay minimization of general networks for heterogeneous FPGA designs with bounded resources. We have tested BinaryHM and CN-HM on MONO benchmarks on Altera FLEX10K device family, which can be taken as the heterogeneous FPGAs with 4-LUTs and a limited number of 11-LUTs. The experimental results show that compared with FlowMap using only 4-LUTs, both BinaryHM and CN-HM can reduce more than 20% of the circuit mapping delays, 27% of the 4-LUT area and 10% of the circuit layout delays by making efficient use of the available heterogeneous LUTs.","PeriodicalId":224802,"journal":{"name":"1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129524723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 21

Finding all simple disjunctive decompositions using irredundant sum-of-products forms 用无冗余乘积和形式找到所有简单析取分解

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) Pub Date : 1998-11-01 DOI: 10.1145/288548.288586

S. Minato, G. Micheli

引用次数: 41