Architecture driven circuit partitioning

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) Pub Date : 1998-11-01 DOI:10.1145/288548.289062

Chau-Shen Chen, TingTing Hwang, C. L. Liu

引用次数: 8

Abstract

We propose an architecture driven partitioning algorithm for netlists with multi terminal nets. Our target architecture is a multi FPGA emulation system with folded Clos network for board routing. Our goal is to minimize the number of FPGA chips used and maximize the routability. To that end, we introduce a new cost function: the average number of pseudo terminals per net in a multi way cut. Experiment result shows that our algorithm is very effective in terms of the number of chips used and the routability as compared to other methods.

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架构驱动电路划分

提出了一种结构驱动的多终端网络划分算法。我们的目标架构是一个多FPGA仿真系统，采用折叠Clos网络进行板路由。我们的目标是尽量减少使用的FPGA芯片数量，并最大限度地提高可达性。为此，我们引入了一个新的成本函数:在多路切割中每个网络的伪终端的平均数量。实验结果表明，与其他方法相比，我们的算法在芯片数量和路由可达性方面是非常有效的。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)

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