Architecture driven circuit partitioning

We propose an architecture driven partitioning algorithm for netlists with multi terminal nets. Our target architecture is a multi FPGA emulation system with folded Clos network for board routing. Our goal is to minimize the number of FPGA chips used and maximize the routability. To that end, we introduce a new cost function: the average number of pseudo terminals per net in a multi way cut. Experiment result shows that our algorithm is very effective in terms of the number of chips used and the routability as compared to other methods.