Hardware/software co-synthesis with memory hierarchies

Abstract

The paper introduces the first hardware/software co-synthesis algorithm of distributed real time systems that optimizes memory hierarchy along with the rest of the architecture. Our algorithm synthesize a set of real time tasks with data dependencies onto a heterogeneous multiprocessor architecture that meets the performance constraints with minimized cost. Our algorithm chooses cache sizes and allocates tasks to caches as part of co-synthesis. Experimental results, including examples from the literature and results on an MPEG-2 encoder, show that our algorithm is efficient and compared with existing algorithms, and it can reduce the overall cost of the synthesized system.