Synthesis of BIST hardware for performance testing of MCM interconnections

Abstract

The issue of performance testing of MCM interconnections is becoming very important due to the fact that hitherto "second order" effects such as ground bounce, crosstalk and switching noise are playing dominant roles in current design methods due to shrinking dimensions, lower supply voltages, higher clock speeds and higher density packaging. We propose a novel scheme for synthesizing nonlinear feedback shift register structures that can be superimposed on the boundary scan cells of ICs to generate MCM interconnect switching activities that resemble real life interconnect switching profiles. The goal is to perform at speed MCM interconnect test while simultaneously capturing the dynamic switching effects referred to earlier as accurately as possible during interconnect BIST. A library of nonlinear feedback shift register structures called Precharacterized Test Pattern Generators (P-TPG) is constructed. Components of P-TPGs are interconnected together in specific ways to recreate the switching activity profile of the interconnections being tested. An optimization algorithm for matching the P-TPG component activity profiles with those of the interconnections under test has been designed, and implemented experimental results confirm the validity of our approach.