The channeled-BSG: a universal floorplan for simultaneous place/route with IC applications

Abstract

The BSG based packing of rectangles has been shown a breakthrough in problem size and generality, if routing is not involved. In order to include the routing, we define the channeled-BSG by associating the BSG-segs with channels. On the channeled-BSG, a new operation, flip, transforms an initial routing to another. Together with a formula that estimates the worst case width of channels for a given global routing, a solution space of simultaneous placement and routing is realized. It is proved that the space contains an optimal solution within the framework of the model. To search the space for a better solution, simulated annealing is implemented. Experiments to industrial data of analog LSIs showed a promising performance.