1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)最新文献_第5页

Transforming control-flow intensive designs to facilitate power management 转换控制流密集的设计，以方便电源管理

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) Pub Date : 1998-11-01 DOI: 10.1145/288548.289107

G. Lakshminarayana, A. Raghunathan, N. Jha, S. Dey

引用次数: 10

h-gamma: an RC delay metric based on a gamma distribution approximation of the homogeneous response 基于齐次响应的伽玛分布近似的RC延迟度量

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) Pub Date : 1998-11-01 DOI: 10.1145/288548.288555

Tao Lin, Emrah Acar, L. Pileggi

{"title":"h-gamma: an RC delay metric based on a gamma distribution approximation of the homogeneous response","authors":"Tao Lin, Emrah Acar, L. Pileggi","doi":"10.1145/288548.288555","DOIUrl":"https://doi.org/10.1145/288548.288555","url":null,"abstract":"Recently a probability interpretation of moments was proposed as a compromise between the Elmore delay and higher order moment matching for RC timing estimation (Kay and Pileggi, 1998). By modeling RC impulses as time-shifted incomplete gamma distribution function, the delays could be obtained via table lookup using a gamma integral table and the first three moments of the impulse response. However, while this approximation works well for many examples, it struggles with responses when the metal resistance becomes dominant, and produces results with impractical time shift values In this paper the probability interpretation is extended to the circuit homogeneous response, without requiring the time shift parameter. The gamma distribution is used to characterize the normalized homogeneous portion of the step response. For a generalized RC interconnect model (RC tree or mesh), the stability of the homogeneous-gamma distribution model is guaranteed. It is demonstrated that when a table model is carefully constructed, the h-gamma approximation provides for excellent improvement over the Elmore delay in terms of accuracy, with very little additional cost in terms of CPU time.","PeriodicalId":224802,"journal":{"name":"1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)","volume":"1063 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116292815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 92

Waiting false path analysis of sequential logic circuits for performance optimization 基于时序逻辑电路性能优化的等待假路径分析

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) Pub Date : 1998-11-01 DOI: 10.1145/288548.289059

Kazuhiro Nakamura, K. Takagi, S. Kimura, Katsumasa Watanabe

引用次数: 18

Reencoding for cycle-time minimization under fixed encoding length 在固定编码长度下，为循环时间最小化而重新编码

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) Pub Date : 1998-11-01 DOI: 10.1145/288548.288631

B. Iyer, M. Ciesielski

{"title":"Reencoding for cycle-time minimization under fixed encoding length","authors":"B. Iyer, M. Ciesielski","doi":"10.1145/288548.288631","DOIUrl":"https://doi.org/10.1145/288548.288631","url":null,"abstract":"The paper presents efficient reencoding and resynthesis algorithms for cycle time minimization of multilevel implementations of synchronous finite state machines (FSMs) under a fixed encoding length. The proposed technique is applicable to both gate level and technology independent synchronous network representations. We present two algorithms for identifying useful reencodings-one is based on Boolean cube representation applicable to technology independent synchronous networks and the other employs recursive learning techniques appropriate for gate netlists. We show that the proposed XOR/XNOR based reencoding technique explores a sufficiently rich set of encodings to identify implementations with smaller cycle times. The Boolean and structural interpretations of reencoding are explored and its relationship to isomorphic sequentially redundant faults is presented. We also show that the reencoded circuit always has a valid initial state and present a simple procedure to derive it. The effectiveness of the proposed technique is illustrated on a large set of benchmark circuits which indicates an average cycle time improvement of 15.26% for a small area overhead of 3.56% over that of performance driven combinational logic optimization.","PeriodicalId":224802,"journal":{"name":"1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126008998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Reduced-order modelling of linear time-varying systems 线性时变系统的降阶建模

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) Pub Date : 1998-11-01 DOI: 10.1145/288548.288581

J. Roychowdhury

引用次数: 36

CONCERT: a concurrent transient fault simulator for nonlinear analog circuits CONCERT:用于非线性模拟电路的并发暂态故障模拟器

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) Pub Date : 1998-11-01 DOI: 10.1145/288548.289058

J. Hou, A. Chatterjee

引用次数: 19

Improving the computational performance of ILP-based problems 提高基于ilp问题的计算性能

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) Pub Date : 1998-11-01 DOI: 10.1145/288548.289091

M. Narasimhan, J. Ramanujam

{"title":"Improving the computational performance of ILP-based problems","authors":"M. Narasimhan, J. Ramanujam","doi":"10.1145/288548.289091","DOIUrl":"https://doi.org/10.1145/288548.289091","url":null,"abstract":"Many interesting problems in VLSI design are computationally extremely difficult, and as such, there exist no efficient (read polynomial time) algorithms for these problems. Such problems include placement, routing, scheduling and partitioning. A commonly used technique for solving these problems is to model them as an integer linear programming (ILP) problem, and to then solve the resulting model using a generic ILP solver. So far, improving the computational efficiency of these problems was considered equivalent to improving the model. We show that large performance improvements can be achieved by incorporating problem specific information into the ILP solver itself. While the techniques that we present are general in nature, for the sake of concreteness, we illustrate them by applying them to scheduling problems in high level synthesis. It is shown that there is a lot of problem specific information that can be incorporated into the model solver, and that doing so actually improves the performance considerably. We present experimental results to show that the problem specific ILP solver is considerably faster, often showing improvements by a factor of 1000 in execution time.","PeriodicalId":224802,"journal":{"name":"1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130309875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Robust latch mapping for combinational equivalence checking 组合等价检验的鲁棒锁存器映射

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) Pub Date : 1998-11-01 DOI: 10.1145/288548.289087

J. Burch, V. Singhal

引用次数: 31

Shaping a VLSI wire to minimize delay using transmission line model

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) Pub Date : 1998-11-01 DOI: 10.1145/288548.289096

Youxin Gao, D. F. Wong

引用次数: 24

High-order Nystrom schemes for efficient 3-D capacitance extraction 用于高效三维电容提取的高阶Nystrom方案

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) Pub Date : 1998-11-01 DOI: 10.1145/288548.288604

S. Kapur, D. Long

引用次数: 20